--===========================================================================----                                                                           ----  S Y N T H E S I Z A B L E    FIR filter   C O R E                        ----                                                                           ----  www.opencores.org - January 2000                                         ----  This IP core adheres to the GNU public license.                          ----                                                                           ----  VHDL model of Finite Impulse Response filter                             ----                                                                           ----  This model uses dual-port memory for storing coefficients and samples.   ----  Resolution of coefficients and samples is adjustable. Number of TAPs     ----  depends on dual-port memory size. This design can be cascaded to         ----  form FIR filter with even greater number of TAPS.                        ----                                                                           ----  Implementation with 16x16 bit fixed point multiplier in Xilinx Virtex    ----  XCV50-6 runs at 55 MHz and with 256 TAPs can handle frequency            ----  bandwidth of +-107KHz.                                                   ----                                                                           ----  Author: Damjan Lampret, lampret@opencores.org                            ----                                                                           ----  TO DO:                                                                   ----                                                                           ----   - synthesis with Syplify pending (there are some problems with          ----     UNSIGNED and BIT_LOGIC_VECTOR types in some units !)                  ----                                                                           ----   - testbench                                                             ----                                                                           ----   - support for more dual-port memories (currently supported              ----     Virtex/Spartan2 (generic dual-port memory added but not tested))      ----                                                                           ----   - top level "cascade" module for easy cascading several FIR filters     ----                                                                           ----   - verification with real application and real coefficients              ----                                                                           ----===========================================================================--library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.config.all;entity mac is    port (	COEFF_IN  : in SIGNED (COEFF_WIDTH-1 downto 0);	SAMPLE_IN : in SIGNED (INPUT_WIDTH-1 downto 0);	OUTPUT : out STD_LOGIC_VECTOR (COEFF_WIDTH+INPUT_WIDTH+TAPS-1 downto 0);	RESTART : in STD_LOGIC;	CLK : in STD_LOGIC;	RST : in STD_LOGIC    );end mac;architecture mac_behav of mac issignal PRODUCT: SIGNED (COEFF_WIDTH+INPUT_WIDTH-1 downto 0);beginmultiply:process(CLK,RST)variable coeff: SIGNED (COEFF_WIDTH-1 downto 0);variable sample: SIGNED (INPUT_WIDTH-1 downto 0);begin	if RST = '1' then		coeff := (others => '0');		sample := (others => '0');		PRODUCT <= (others => '0');	elsif rising_edge(CLK) then		coeff := COEFF_IN;		sample := SAMPLE_IN;		PRODUCT <= coeff * sample;	end if;end process;accumulate:process(CLK,RST)variable sum: SIGNED (COEFF_WIDTH+INPUT_WIDTH+TAPS-1 downto 0);begin	if RST = '1' then		sum := (others => '0');		OUTPUT <= (others => '0');	elsif rising_edge(CLK) then		if RESTART = '1' then			OUTPUT <= MAKE_BINARY(sum);			sum := (others => '0');		else			sum := sum + PRODUCT;		end if;	end if;end process;end mac_behav;