--===========================================================================----                                                                           ----  S Y N T H E S I Z A B L E    FIR filter   C O R E                        ----                                                                           ----  www.opencores.org - January 2000                                         ----  This IP core adheres to the GNU public license.                          ----                                                                           ----  VHDL model of Finite Impulse Response filter                             ----                                                                           ----  This model uses dual-port memory for storing coefficients and samples.   ----  Resolution of coefficients and samples is adjustable. Number of TAPs     ----  depends on dual-port memory size. This design can be cascaded to         ----  form FIR filter with even greater number of TAPS.                        ----                                                                           ----  Implementation with 16x16 bit fixed point multiplier in Xilinx Virtex    ----  XCV50-6 runs at 55 MHz and with 256 TAPs can handle frequency            ----  bandwidth of +-107KHz.                                                   ----                                                                           ----  Author: Damjan Lampret, lampret@opencores.org                            ----                                                                           ----  TO DO:                                                                   ----                                                                           ----   - synthesis with Syplify pending (there are some problems with          ----     UNSIGNED and BIT_LOGIC_VECTOR types in some units !)                  ----                                                                           ----   - testbench                                                             ----                                                                           ----   - support for more dual-port memories (currently supported              ----     Virtex/Spartan2 (generic dual-port memory added but not tested))      ----                                                                           ----   - top level "cascade" module for easy cascading several FIR filters     ----                                                                           ----   - verification with real application and real coefficients              ----                                                                           ----===========================================================================--library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.config.all;entity dpmem is    port (	ADDRA : in UNSIGNED (MAXMEMADDR-1 downto 0);	ADDRB : in UNSIGNED (MAXMEMADDR-1 downto 0);	DIA : in STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);	DIB : in STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);	DOA : out STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);	DOB : out STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);	CLKA : in STD_LOGIC;	CLKB : in STD_LOGIC;	ENA : in STD_LOGIC;	ENB : in STD_LOGIC;	RSTA : in STD_LOGIC;	RSTB : in STD_LOGIC;	WEA : in STD_LOGIC;	WEB : in STD_LOGIC    );end dpmem;architecture dpram of dpmem istype mem_type is array (NUM_TAPS downto 0) of std_logic_vector (MAXMEMWIDTH-1 downto 0);signal memarray : mem_type;signal PORTA, PORTB: std_logic_vector (MAXMEMWIDTH-1 downto 0);beginporta_dpmem_ctrl:process(CLKA,RSTA)begin	if RSTA = '1' then	elsif rising_edge(CLKA) then		if ENA = '1' then			if WEA = '1' then				PORTA <= DIA;			end if;			DOA <= memarray(conv_integer(ADDRA));		end if;	end if;end process;portb_dpmem_ctrl:process(CLKB,RSTB)begin	if RSTB = '1' then	elsif rising_edge(CLKB) then		if ENB = '1' then			if WEB = '1' then				PORTB <= DIB;			end if;			DOB <= memarray(conv_integer(ADDRB));		end if;	end if;end process;join_writes:process(PORTA,PORTB)begin	if WEA = '1' then		memarray(conv_integer(ADDRA)) <= PORTA;	elsif WEB = '1' then		memarray(conv_integer(ADDRB)) <= PORTB;	end if;end process;end dpram;