--===========================================================================----                                                                           ----  S Y N T H E S I Z A B L E    FIR filter   C O R E                        ----                                                                           ----  www.opencores.org - January 2000                                         ----  This IP core adheres to the GNU public license.                          ----                                                                           ----  VHDL model of Finite Impulse Response filter                             ----                                                                           ----  This model uses dual-port memory for storing coefficients and samples.   ----  Resolution of coefficients and samples is adjustable. Number of TAPs     ----  depends on dual-port memory size. This design can be cascaded to         ----  form FIR filter with even greater number of TAPS.                        ----                                                                           ----  Implementation with 16x16 bit fixed point multiplier in Xilinx Virtex    ----  XCV50-6 runs at 55 MHz and with 256 TAPs can handle frequency            ----  bandwidth of +-107KHz.                                                   ----                                                                           ----  Author: Damjan Lampret, lampret@opencores.org                            ----                                                                           ----  TO DO:                                                                   ----                                                                           ----   - synthesis with Syplify pending (there are some problems with          ----     UNSIGNED and BIT_LOGIC_VECTOR types in some units !)                  ----                                                                           ----   - testbench                                                             ----                                                                           ----   - support for more dual-port memories (currently supported              ----     Virtex/Spartan2 (generic dual-port memory added but not tested))      ----                                                                           ----   - top level "cascade" module for easy cascading several FIR filters     ----                                                                           ----   - verification with real application and real coefficients              ----                                                                           ----===========================================================================--library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use work.config.all;entity coeff_dpmem is    port (	INPUT  : in STD_LOGIC_VECTOR (COEFF_WIDTH-1 downto 0);	OUTPUT : out STD_LOGIC_VECTOR (COEFF_WIDTH-1 downto 0);	REPEAT : out STD_LOGIC;	LOADING_COEFF : out STD_LOGIC;	CLK : in STD_LOGIC;	RST : in STD_LOGIC    );end coeff_dpmem;architecture virtex_blockram of coeff_dpmem iscomponent RAMB4_S16_S16    port (	ADDRA : in UNSIGNED (MAXMEMADDR-1 downto 0);	ADDRB : in UNSIGNED (MAXMEMADDR-1 downto 0);	DIA : in STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);	DIB : in STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);--	DOA : out STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);	DOB : out STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);	CLKA : in STD_LOGIC;	CLKB : in STD_LOGIC;	ENA : in STD_LOGIC;	ENB : in STD_LOGIC;	RSTA : in STD_LOGIC;	RSTB : in STD_LOGIC;	WEA : in STD_LOGIC;	WEB : in STD_LOGIC    );end component;attribute INIT_00 : string;attribute INIT_00 of virtex_blockram: label is "000100020003000400050006000000000000000000000000000000000000000F";signal WRITE_ADDR: UNSIGNED (MAXMEMADDR-1 downto 0);signal WRITE_DATA: STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);signal READ_ADDR: UNSIGNED (MAXMEMADDR-1 downto 0);signal READ_DATA: STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);signal RD: STD_LOGIC;signal WR: STD_LOGIC;signal GND: STD_LOGIC_VECTOR (MAXMEMWIDTH-1 downto 0);beginGND <= (others => '0');LOADING_COEFF <= WR;    OUTPUT (COEFF_WIDTH-1 downto 0) <= READ_DATA (COEFF_WIDTH-1 downto 0);WRITE_DATA (COEFF_WIDTH-1 downto 0) <= INPUT (COEFF_WIDTH-1 downto 0);    coeff_dpmem_ctrl:process(CLK,RST)variable counter: UNSIGNED (TAPS downto 0);begin	if RST = '1' then		counter := (others => '0');		WR <= not COEFF_LOADED_AT_STARTUP;		RD <= '0';	elsif rising_edge(CLK) then		if counter < NUM_TAPS then			counter := counter + 1;			REPEAT <= '0';					elsif counter = NUM_TAPS then			counter := (others => '0');			REPEAT <= '1';			WR <= '0';		else		end if;		READ_ADDR (MAXMEMADDR-1 downto TAPS) <= (others => '0');		WRITE_ADDR (MAXMEMADDR-1 downto TAPS) <= (others => '0');		READ_ADDR (TAPS-1 downto 0) <= counter (TAPS-1 downto 0);		WRITE_ADDR (TAPS-1 downto 0) <= counter (TAPS-1 downto 0);	end if;end process;virtex_blockram: RAMB4_S16_S16    port map(	ADDRA => WRITE_ADDR,	ADDRB => READ_ADDR,	DIA => WRITE_DATA,	DIB => GND,--	DOA => open,	DOB => READ_DATA,	CLKA => CLK,	CLKB => CLK,	ENA => WR,	ENB => RD,	RSTA => RST,	RSTB => RST,	WEA => WR,	WEB => GND(0)    );end virtex_blockram;