-- This VHDL Source Have been create with WITHCLASS95
-- Scrip file written by Clerbois M

package ADDER4PKG is
    COMPONENT ADDER4
	PORT (
--	CLOCK,RESET:IN BIT; only for synchronous object
  A :  IN BIT_VECTOR(0TO3 ) ;
  B :  IN BIT_VECTOR(0TO3) ;
  S :  OUTBV (0TO3) ;
  Cout :  OUT BIT  );
	END ADDER4;
END ADDER4PKG;

ENTITY  ADDER4 is 
	PORT (
--	CLOCK,RESET:IN BIT; only for synchronous object
 	 A :  IN BIT_VECTOR(0TO3 ) ;
 	 B :  IN BIT_VECTOR(0TO3) ;
 	 S :  OUTBV (0TO3) ;
 	 Cout :  OUT BIT  );
	END ADDER4;
END ADDER4;

ARCHITECTURE FSMADDER4 OF ADDER4 IS
 
 

--BEGIN
--Insert NOT State machine Process here
-- process ()

-- AGGREGATION of ONE TO MANY == instantation of object
-- copy the lines N times and modify the parameters
 ADD : FullAdder ( -- list of signals ) ; 

-- AGGREGATION of ONE TO ONE == instantation of an object
-- Generate the instantiation line and modify the parameters
 MMM : Bidon ( -- list of signals ) ; 



-- begin
-- end process;

-- Insert here the process source file generated with state code report (cut and paste)
-- Use the script file vhdlst.sct to generate the state machine

END FSMADDER4;