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--
-- Title       : No Title
-- Design      : gateway
-- Author      : zlm
-- Company     : buaa
--
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--
-- File        : d:\My_Designs\gateway\gateway\compile\synchronizer.vhd
-- Generated   : 12/15/04 00:54:07
-- From        : d:\My_Designs\gateway\gateway\src\synchronizer.asf
-- By          : FSM2VHDL ver. 4.0.3.8
--
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--
-- Description : 
--
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity synchronizer is 
	port (
		reset:in STD_LOGIC;
		clk: in STD_LOGIC;
		din:in STD_LOGIC;
		dout:out STD_LOGIC;
		gate:out STD_LOGIC);
end;

architecture synchronizer_arch of synchronizer is

	constant framecode:std_logic_vector(7 downto 0):="11110110";
	
	type Sreg0_type is (lost, check, protect, syn);
	signal Sreg0: Sreg0_type; 
	
	type Sreg1_type is (S0,S1,S2,S3,S4,S5,S6,S7);
	signal Sreg1:Sreg1_type;
	
	signal flag:std_logic_vector(2 downto 0);
	signal clk_8k:std_logic;

begin

process(clk,reset) 
variable cnt:integer range 0 to 255; 

begin
	if reset='1'then 
		clk_8k<='0';
		cnt:=0;
	elsif clk='1'and clk'event then
		if cnt=127 then
			clk_8k<='0';
			cnt:=cnt+1;
		elsif cnt=255 then
			clk_8k<='1';
			cnt:=0;		
		else	
			cnt:=cnt+1;
		end if;	
	end if;	
end process;


process(clk,reset)
begin
	if reset='1' then
		Sreg1<=S0;
		flag(0)<='0';
	elsif clk'event and clk='1'then
		case Sreg1 is
			when S0 =>
				if din=framecode(0) then
					Sreg1 <= S1;
					flag(0)<='0';
				else
					Sreg1 <= S0;
					flag(0)<='0';
				end if;	
			when S1 =>
				if din=framecode(1) then
					Sreg1 <= S2;
				else
					Sreg1 <= S1;
				end if;
			when S2 =>
				if din=framecode(2) then
					Sreg1 <= S3;
				else
					Sreg1 <= S1;
				end if;	
			when S3 =>
				if din=framecode(3) then
					Sreg1 <= S4;
				else
					Sreg1 <= S0;
				end if;	
			when S4 =>
				if din=framecode(4) then
					Sreg1 <= S5;
				else
					Sreg1 <= S1;
				end if;	
			when S5 =>
				if din=framecode(5) then
					Sreg1 <= S6;
				else
					Sreg1 <= S1;
				end if;	 
			when S6 =>
				if din=framecode(6) then
					Sreg1 <= S7;
				else
					Sreg1 <= S1;
				end if;	
			when S7 =>
				if din=framecode(7) then
					Sreg1 <= S0;
					flag(0)<='1';
				else
					Sreg1 <= S1;
				end if;
			when others =>
					null;
		end case;	
	end if;			
end process;


process (clk,flag(0),reset) 

variable cnt:integer range 0 to 255;

begin
	if reset='1'then
		flag(1)<='0';
		cnt:=0;
	elsif flag(0)'event and flag(0)='1'then
		flag(1)<='1';
		cnt:=1;
	elsif clk'event and clk='1'then
		if cnt=255 then
			flag(1)<='0';
			cnt:=0;
		else
			cnt:=cnt+1;
		end if; 
	end if;
end process;
	


process (clk_8k,reset)

variable cnt:integer range 1 to 3;

begin
	if reset='1' then
		cnt:=1;
		Sreg0 <= lost;
		flag(2)<='0';
	elsif clk_8k'event and clk_8k = '1' then
		case Sreg0 is
			when lost =>
				if flag(1)='1' then	
					Sreg0 <= check;	
				end if;
			when check =>
				if flag(1)='1' then
					if cnt=2 then
						Sreg0 <= syn;
						flag(2)<='1';
						cnt:=1;
					else
					   cnt:=cnt+1;
					end if;
				else	
					Sreg0 <= lost;
					cnt:=1;
				end if;
			when protect =>
				if flag(1)='1' then	
					Sreg0 <= syn;
					flag(2)<='1';
					cnt:=1;
				else
					if cnt=3 then
						Sreg0 <= lost;
						cnt:=1;
					else
						cnt:=cnt+1;
					end if;
				end if;
			when syn =>
				if flag(1)='0' then	
					Sreg0 <= protect;
					flag(2)<='0';
				end if;
			when others =>
				null;
		end case;
	end if;
end process; 


process (clk,flag(0),reset) 

variable cnt:integer range 0 to 247;

begin
	if reset='1'then
		gate<='0';
		cnt:=0;
	elsif flag(0)'event and flag(0)='1'then
		if flag(2)='1' then
			gate<='1';
			cnt:=0;	
		end if;
	elsif clk'event and clk='1'then
		if cnt=247 then
			gate<='0';
			cnt:=0;
		else
			cnt:=cnt+1;
		end if; 
	end if;
end process;


process(din,reset)
begin
	if reset='1'then
		dout<='0';
	else	
		dout<=din;
	end if;	
end process;

end synchronizer_arch;