/*
 * memsetup-sa1100.S: memory setup for various SA1100 architectures
 *
 * $Id: memsetup-sa1100.S,v 1.2 2001/11/04 23:16:26 erikm Exp $
 *
 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */
/*
 * Documentation:
 * Intel Corporation, "Intel StrongARM SA-1100 Microprocessor
 *     Developer's Manual", April 1999
 */

.ident "$Id: memsetup-sa1100.S,v 1.2 2001/11/04 23:16:26 erikm Exp $"

#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif

#include <blob/arch.h>



.text




MEM_BASE:	.long	0xa0000000
MEM_START:	.long	MEMORY_START
#define	MDCNFG	0x0
#define MDCAS0	0x04
#define MDCAS1	0x08
#define MDCAS2	0x0c
#define MCS0	0x10




#if (defined BRUTUS)
mdcas0:		.long	0xc71c703f
mdcas1:		.long	0xffc71c71
mdcas2:		.long	0xffffffff
mdcnfg:		.long	0x0334b22f
mcs0:		.long	0xfff8fff8
#endif

#if (defined NESA)
mdcas0:		.long	0xc71c703f
mdcas1:		.long	0xffc71c71
mdcas2:		.long	0xffffffff
mdcnfg:		.long	0x0334b22f
mcs0:		.long	0xfff84458
#endif

#if defined LART
mdcas0:		.long	0xc71c703f
mdcas1:		.long	0xffc71c71
mdcas2:		.long	0xffffffff
mdcnfg:		.long	0x0334b22f
mcs0:		.long	0xad8c4888
#endif

#if defined PLEB
mdcas0:		.long	0x8e38e01f
mdcas1:		.long	0xff8e38e3
mdcas2:		.long	0xffffffff
mdcnfg:		.long	0x0bb2bcbf
mcs0:		.long	0xfff8fff8
#endif

#if defined SHANNON
mdcas0:		.long	0xc71c703f
mdcas1:		.long	0xffc71c71
mdcas2:		.long	0xffffffff
mdcnfg:		.long	0x0334b21f
mcs0:		.long	0xfff84458
#endif




.globl memsetup
memsetup:
	/* Setup the flash memory */
	ldr	r0, MEM_BASE
	
	ldr	r1, mcs0
	str	r1, [r0, #MCS0]
	
	/* Set up the DRAM */
	
	/* MDCAS0 */
	ldr	r1, mdcas0
	str	r1, [r0, #MDCAS0]

	/* MDCAS1 */
	ldr	r1, mdcas1
	str	r1, [r0, #MDCAS1]

	/* MDCAS2 */
	ldr	r1, mdcas2
	str	r1, [r0, #MDCAS2]

	/* MDCNFG */
	ldr	r1, mdcnfg
	str	r1, [r0, #MDCNFG]

	/* Issue read requests to disabled bank to start refresh */
	/* this is required by the Micron memory on a TuxScreen */
	
	/* Comment from JDB:
	 * This is not strictly necessary. As long as blob writes something to
	 * the serial port between enabling and accessing DRAM (as I think it
	 * does even on Shannon), you can pretty much guarantee that the
	 * required eight refreshes have occurred (as 1 refresh is ~16
	 * microseconds, so even writing two characters at 115k2 covers the
	 * refreshes).
	 *
	 * Comment (on comment) from Erik:
	 * We don't print anymore in the low level loader, so we need this
	 * on all architectures.
	 */
	ldr	r1, MEM_START

.rept	8
	ldr	r0, [r1]
.endr
	
	mov	pc, lr