?? vrc4373_serial.c
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//==========================================================================//// io/serial/mips/vrc4373_serial.c//// Mips VRC4373 Serial I/O Interface Module (interrupt driven)////==========================================================================//####COPYRIGHTBEGIN####// // ------------------------------------------- // The contents of this file are subject to the Red Hat eCos Public License // Version 1.1 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://www.redhat.com/ // // Software distributed under the License is distributed on an "AS IS" // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the // License for the specific language governing rights and limitations under // the License. // // The Original Code is eCos - Embedded Configurable Operating System, // released September 30, 1998. // // The Initial Developer of the Original Code is Red Hat. // Portions created by Red Hat are // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. // All Rights Reserved. // ------------------------------------------- // //####COPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s): gthomas// Contributors: gthomas// Date: 1999-04-15// Purpose: VRC4373 Serial I/O module (interrupt driven version)// Description: ////####DESCRIPTIONEND####//==========================================================================#include <pkgconf/system.h>#include <pkgconf/io_serial.h>#include <pkgconf/io.h>#include <cyg/io/io.h>#include <cyg/hal/hal_intr.h>#include <cyg/io/devtab.h>#include <cyg/io/serial.h>#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373#include "vrc4373_serial.h"#if defined(CYGPKG_HAL_MIPS_LSBFIRST)#define VRC4373_SCC_BASE 0xC1000000#elif defined(CYGPKG_HAL_MIPS_MSBFIRST)#define VRC4373_SCC_BASE 0xC1000003#else#error MIPS endianness not defined by configuration#endif#define VRC4373_SCC_INT CYGNUM_HAL_INTERRUPT_DUART#define SCC_CHANNEL_A 4#define SCC_CHANNEL_B 0extern void diag_printf(const char *fmt, ...);typedef struct vrc4373_serial_info { CYG_ADDRWORD base; unsigned char regs[16]; // Known register state (since hardware is write-only!)} vrc4373_serial_info;static bool vrc4373_serial_init(struct cyg_devtab_entry *tab);static bool vrc4373_serial_putc(serial_channel *chan, unsigned char c);static Cyg_ErrNo vrc4373_serial_lookup(struct cyg_devtab_entry **tab, struct cyg_devtab_entry *sub_tab, const char *name);static unsigned char vrc4373_serial_getc(serial_channel *chan);static bool vrc4373_serial_set_config(serial_channel *chan, cyg_serial_info_t *config);static void vrc4373_serial_start_xmit(serial_channel *chan);static void vrc4373_serial_stop_xmit(serial_channel *chan);static cyg_uint32 vrc4373_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);static void vrc4373_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);static SERIAL_FUNS(vrc4373_serial_funs, vrc4373_serial_putc, vrc4373_serial_getc, vrc4373_serial_set_config, vrc4373_serial_start_xmit, vrc4373_serial_stop_xmit );#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0static vrc4373_serial_info vrc4373_serial_info0 = {VRC4373_SCC_BASE+SCC_CHANNEL_A};#if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE > 0static unsigned char vrc4373_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE];static unsigned char vrc4373_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BUFSIZE];static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel0, vrc4373_serial_funs, vrc4373_serial_info0, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT, &vrc4373_serial_out_buf0[0], sizeof(vrc4373_serial_out_buf0), &vrc4373_serial_in_buf0[0], sizeof(vrc4373_serial_in_buf0) );#elsestatic SERIAL_CHANNEL(vrc4373_serial_channel0, vrc4373_serial_funs, vrc4373_serial_info0, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL0_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT );#endifDEVTAB_ENTRY(vrc4373_serial_io0, CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL0_NAME, 0, // Does not depend on a lower level interface &cyg_io_serial_devio, vrc4373_serial_init, vrc4373_serial_lookup, // Serial driver may need initializing &vrc4373_serial_channel0 );#endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1static vrc4373_serial_info vrc4373_serial_info1 = {VRC4373_SCC_BASE+SCC_CHANNEL_B};#if CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE > 0static unsigned char vrc4373_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE];static unsigned char vrc4373_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BUFSIZE];static SERIAL_CHANNEL_USING_INTERRUPTS(vrc4373_serial_channel1, vrc4373_serial_funs, vrc4373_serial_info1, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT, &vrc4373_serial_out_buf1[0], sizeof(vrc4373_serial_out_buf1), &vrc4373_serial_in_buf1[0], sizeof(vrc4373_serial_in_buf1) );#elsestatic SERIAL_CHANNEL(vrc4373_serial_channel1, vrc4373_serial_funs, vrc4373_serial_info1, CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC4373_SERIAL1_BAUD), CYG_SERIAL_STOP_DEFAULT, CYG_SERIAL_PARITY_DEFAULT, CYG_SERIAL_WORD_LENGTH_DEFAULT, CYG_SERIAL_FLAGS_DEFAULT );#endifDEVTAB_ENTRY(vrc4373_serial_io1, CYGDAT_IO_SERIAL_MIPS_VRC4373_SERIAL1_NAME, 0, // Does not depend on a lower level interface &cyg_io_serial_devio, vrc4373_serial_init, vrc4373_serial_lookup, // Serial driver may need initializing &vrc4373_serial_channel1 );#endif // CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1static cyg_interrupt vrc4373_serial_interrupt;static cyg_handle_t vrc4373_serial_interrupt_handle;// Table which maps hardware channels (A,B) to software onesstruct serial_channel *vrc4373_chans[] = {#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL0 // Hardware channel A &vrc4373_serial_channel0, #else 0,#endif#ifdef CYGPKG_IO_SERIAL_MIPS_VRC4373_SERIAL1 // Hardware channel B &vrc4373_serial_channel1,#else 0,#endif};// Support functions which access the serial device. Note that this chip requires// a substantial delay after each access. #define SCC_DELAY 100inline static voidscc_delay(void){ int i; for (i = 0; i < SCC_DELAY; i++) ;}inline static voidscc_write_reg(volatile unsigned char *reg, unsigned char val){ scc_delay(); *reg = val;}inline static unsigned charscc_read_reg(volatile unsigned char *reg){ unsigned char val; scc_delay(); val = *reg; return (val);}inline static unsigned charscc_read_ctl(volatile struct serial_port *port, int reg){ if (reg != 0) { scc_write_reg(&port->scc_ctl, reg); } return (scc_read_reg(&port->scc_ctl));}inline static voidscc_write_ctl(volatile struct serial_port *port, int reg, unsigned char val){ if (reg != 0) { scc_write_reg(&port->scc_ctl, reg); } scc_write_reg(&port->scc_ctl, val);}
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