// Xilinx Verilog produced by program ngd2ver, Version M1.4.12// Date: Tue Jan  6 18:46:27 1998// Design file: time_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd  module gate_reduce (A_CHECK, B_CHECK, RESET, CLOCK, CLKEN, A_TICK, B_TICK,   ST_A, ST_B);    input A_CHECK;    input B_CHECK;    input RESET;    input CLOCK;    input CLKEN;    input A_TICK;    input B_TICK;    output ST_A;    output ST_B;    wire n59, n60, n61, n62, n63, n64, n65, n438, n439, \I_0/n796 ,     \I_0/ST_INT489 , \I_1/ST_INT489 , n218, n180, n179, \I_0/CLRZERO ,     \I_0/CLRZERO353 , \I_0/n354 , n219, n191, n189, \I_0/n336 , n220,     \I_0/ZCNT_E638 , \I_0/n345 , n221, \I_1/ZCNT_E638 , \I_1/n345 , \I_0/ECNT_E     , \I_0/ECNT_E477 , \I_0/n301 , n222, n176, n223, n144, n173, \I_0/ZCNT_E ,     n224, n225, n190, n226, n186, n231, n230, n229, n227, n228, n198, n234, n233    , n232, n145, \I_1/CLRZERO , \I_1/CLRZERO353 , \I_1/n354 , n235,     \I_1/ECNT_E477 , n237, \I_1/n301 , n236, \I_1/ECNT_E , n201, n238, \I_1/EQ2     , n181, \I_1/n336 , n239, n240, n157, n243, n242, n241, n162, n244, n245,     n246, n155, n249, n248, n247, n141, \I_1/ZCNT_E , n250, n251, n149, n184,     n252, n253, n158, n174, n254, n255, n143, n257, n256, n259, n258, \I_0/n104     , \I_0/E2RQ , n164, n261, n260, n171, n154, n262, n263, n163, n264, n265,     n266, n148, \I_0/EQ2 , n267, n268, n269, n147, n271, n270, n273, n272,     \I_1/n104 , \I_1/E2RQ , n153, n274, n275, n182, n277, n276, n169, n161, n278    , n279, n152, n280, n281, n282, n284, n283, n285, \I_0/CLREVENT , n286,     \I_0/n319 , n287, n289, n288, n140, n290, n291, n293, n292, n294,     \I_1/CLREVENT , n295, \I_1/n319 , n296, n298, n297, n299, n300, n301, n302,     n303, n304, n306, n305, n307, n308, n309, n310, n311, n312, n314, n313, n315    , n316, n317, n318, n319, n183, n321, n320, n322, n323, n324, n325, n328,     n327, n326, n329, n331, n330, n332, n333, n334, n336, n335, n338, n337, n160    , n339, n341, n340, n159, n346, n342, n344, n343, n345, n347, n349, n348,     n350, n351, n352, n354, n353, n359, n355, n357, n356, n358, n360, n362, n361    , n363, n365, n364, n151, n366, n368, n367, n150, n373, n369, n371, n370,     n372, \I_0/n327 , n374, n172, n378, n377, \I_1/n327 , n379, n380, n383, n382    , n381, n384, n385, n388, n387, n386, n389, n390, n391, n392, n393, n396,     n395, n394, n397, n398, n401, n400, n399, n402, n403, n404, n405, n408, n407    , n406, n412, n409, n410, n411, n413, n418, n414, n417, n416, n415, n419,     n420, n421, n426, n422, n425, n424, n423, n427, n428, n429, n437, n436, n430    , n431, n432, n435, n433, n434, \I_0/CLRZERO_reg_GSR_OR ,     \I_0/ST_INT_reg_GSR_OR , \I_0/ECNT_E_reg_GSR_OR , \I_0/ZCNT_E_reg_GSR_OR ,     \I_0/ECNT_reg[2]_GSR_OR , \I_1/CLRZERO_reg_GSR_OR , \I_1/ST_INT_reg_GSR_OR     , \I_1/ECNT_E_reg_GSR_OR , \I_1/ZCNT_E_reg_GSR_OR , \I_1/DCNT_reg[2]_GSR_OR     , \I_0/ZCNT_reg[1]_GSR_OR , \I_0/ZCNT_reg[2]_GSR_OR ,     \I_0/ECNT_reg[4]_GSR_OR , \I_0/ECNT_reg[1]_GSR_OR , \I_1/ZCNT_reg[1]_GSR_OR     , \I_1/ZCNT_reg[2]_GSR_OR , \I_1/ECNT_reg[4]_GSR_OR ,     \I_1/ECNT_reg[1]_GSR_OR , \I_0/CLREVENT_reg_GSR_OR ,     \I_1/CLREVENT_reg_GSR_OR , \I_1/ZCNT_reg[0]_GSR_OR ,     \I_0/ZCNT_reg[0]_GSR_OR , \I_0/ECNT_reg[0]_GSR_OR , \I_1/ECNT_reg[0]_GSR_OR     , \I_0/E2RQ_reg_GSR_OR , \I_1/ECNT_reg[2]_GSR_OR , \I_1/E2RQ_reg_GSR_OR ,     \I_1/DCNT_reg[0]_GSR_OR , \I_1/ZCNT_reg[4]_GSR_OR , \I_1/ZCNT_reg[6]_GSR_OR     , \I_0/DCNT_reg[0]_GSR_OR , \I_0/DCNT_reg[2]_GSR_OR ,     \I_0/ZCNT_reg[4]_GSR_OR , \I_0/ZCNT_reg[6]_GSR_OR , \I_0/EQ2_reg_GSR_OR ,     \I_1/EQ2_reg_GSR_OR , \I_1/DCNT_reg[1]_GSR_OR , \I_1/ZCNT_reg[3]_GSR_OR ,     \I_1/ZCNT_reg[5]_GSR_OR , \I_0/DCNT_reg[1]_GSR_OR , \I_0/ZCNT_reg[3]_GSR_OR     , \I_0/ZCNT_reg[5]_GSR_OR , \U180/$1I20_GTS_TRI , \U181/$1I20_GTS_TRI ,     \U176/clkio_bufsig , \U186/2_0 , \U187/2_0 , \U189/2_0 , \U190/2_0 ,     \U192/2_0 , \U194/2_0 , \U196/2_0 , \U197/2_0 , \U200/2_0 , \U203/2_0 ,     \U209/2_0 , \U209/2_1 , \U212/2_0 , \U217/2_0 , \U222/2_0 , \U222/2_1 ,     \U225/2_0 , \U230/2_0 , \U233/2_0 , \U237/2_0 , \U237/2_1 , \U240/2_0 ,     \U240/2_1 , \U247/2_0 , \U258/2_0 , \U258/2_1 , \U260/2_0 , \U267/2_0 ,     \U280/2_0 , \U303/2_0 , \U306/2_0 , \U307/2_0 , \U311/2_0 , \U315/2_0 ,     \U324/2_0 , \U389/2_0 , \U389/2_1 , \U399/2_0 , \U399/2_1 , \U402/2_0 ,     \U414/2_0 , \U417/2_0 , \U420/2_0 , \U432/2_0 , \U435/2_0 , \U444/2_0 ,     \U444/2_1 , \U448/2_0 , \U454/2_0 , \U455/2_0 , \U455/2_1 , \U460/2_0 ,     \U466/2_0 , \U467/2_0 , \U467/2_1 , \U474/2_0 , \n171/F , \n171/G ,     \n171/H1 , \n171/H , \n171/H0 , \n171/DFF_OUT/$1N115 , \n171/FGBLOCK/$1N8 ,     \n171/FGBLOCK/$1N18 , \n171/FGBLOCK/LUTRAM/FLUT/AND0 , \n171/HLUT/XOR0 ,     \n169/F , \n169/G , \n169/H1 , \n169/H , \n169/H0 , \n169/DFF_OUT/$1N48 ,     \n169/FGBLOCK/$1N18 , \n169/FGBLOCK/LUTRAM/FLUT/AND0 , \n169/HLUT/XOR0 ,     U201_2_INV, U204_2_INV, U206_2_INV, U215_2_INV, U219_2_INV, U226_2_INV,     U228_2_INV, U229_2_INV, U268_2_INV, U284_2_INV, U285_2_INV, U289_2_INV,     U290_2_INV, U294_2_INV, U295_2_INV, U299_2_INV, U300_2_INV, U302_2_INV,     U305_2_INV, U310_2_INV, U314_2_INV, U322_2_INV, U323_2_INV, U331_2_INV,     U332_2_INV, U333_2_INV, U334_2_INV, U339_2_INV, U342_2_INV, U355_2_INV,     U360_2_INV, U363_2_INV, U370_2_INV, U375_2_INV, U386_2_INV, U397_2_INV,     U403_2_INV, U404_2_INV, U410_2_INV, U411_2_INV, U421_2_INV, U422_2_INV,     U428_2_INV, U429_2_INV, U438_2_INV, U440_2_INV, U445_2_INV, U447_2_INV,     U451_2_INV, U452_2_INV, U457_2_INV, U459_2_INV, U463_2_INV, U464_2_INV,     U472_2_INV, U476_2_INV, U477_2_INV, U478_2_INV, \U187/n179_2_INV ,     \U190/n189_2_INV , \U196/n176_2_INV , \U200/n225_2_INV , \U203/n186_2_INV ,     \U209/n198_2_INV , \U212/n233_2_INV , \U217/n201_2_INV , \U222/n157_2_INV ,     \U225/n242_2_INV , \U230/n155_2_INV , \U233/n248_2_INV , \U247/n164_2_INV ,     \U258/n148_2_INV , \U260/I_0/ZCNT_E638_2_INV , \U267/n153_2_INV ,     \U280/I_1/ZCNT_E638_2_INV , \U303/n302_2_INV , \U306/n306_2_INV ,     \U311/n309_2_INV , \U315/n312_2_INV , \U389/n374_2_INV , \U399/n379_2_INV ,     \U180/$1I20_GTS_TRI_2_INV , \U181/$1I20_GTS_TRI_2_INV , GND;    wire [4:0] \I_1/ECNT ;    wire [4:0] \I_0/ECNT ;    wire [2:0] \I_1/DCNT ;    wire [4:0] \I_1/ZCNT ;    wire [6:2] \I_1/lt_130/AEQB ;    wire [2:0] \I_0/DCNT ;    wire [4:1] \I_0/ECNT110 ;    wire [0:0] \I_0/n362 ;    wire [0:0] \I_1/n310 ;    wire [0:0] \I_0/n310 ;    wire [2:2] \I_1/DCNT480 ;    wire [4:0] \I_0/ZCNT ;    wire [0:0] \I_0/n370 ;    wire [6:2] \I_0/lt_130/AEQB ;    wire [0:0] \I_1/n370 ;    wire [4:1] \I_1/ECNT110 ;    wire [0:0] \I_1/n362 ;    `ifdef GSR_SIGNAL      wire GSR = `GSR_SIGNAL ;    `else      wire GSR ;    `endif    `ifdef GTS_SIGNAL      wire GTS = `GTS_SIGNAL ;    `else      wire GTS ;    `endif    initial $sdf_annotate("time_sim.sdf");    X_BUF U173 (.IN (A_CHECK), .OUT (n59));    X_BUF U174 (.IN (B_CHECK), .OUT (n60));    X_BUF U175 (.IN (RESET), .OUT (n61));    X_BUF U177 (.IN (CLKEN), .OUT (n63));    X_BUF U178 (.IN (A_TICK), .OUT (n64));    X_BUF U179 (.IN (B_TICK), .OUT (n65));    X_INV U182 (.IN (n61), .OUT (\I_0/n796 ));    X_INV U183 (.IN (n438), .OUT (\I_0/ST_INT489 ));    X_INV U184 (.IN (n439), .OUT (\I_1/ST_INT489 ));    X_INV U185 (.IN (\I_1/ECNT [4]), .OUT (n218));    X_FF \I_0/CLRZERO_reg  (.IN (\I_0/CLRZERO353 ), .CLK (n62), .CE (\I_0/n354 )    , .SET (GND), .RST (\I_0/CLRZERO_reg_GSR_OR ), .OUT (\I_0/CLRZERO ));    X_INV U188 (.IN (\I_0/ECNT [4]), .OUT (n219));    X_FF \I_0/ST_INT_reg  (.IN (\I_0/ST_INT489 ), .CLK (n62), .CE (\I_0/n336 ),     .SET (GND), .RST (\I_0/ST_INT_reg_GSR_OR ), .OUT (n438));    X_OR2 U191 (.IN0 (n64), .IN1 (\I_0/ZCNT_E638 ), .OUT (n220));    X_OR2 U193 (.IN0 (n65), .IN1 (\I_1/ZCNT_E638 ), .OUT (n221));    X_FF \I_0/ECNT_E_reg  (.IN (\I_0/ECNT_E477 ), .CLK (n62), .CE (\I_0/n301 ),     .SET (GND), .RST (\I_0/ECNT_E_reg_GSR_OR ), .OUT (\I_0/ECNT_E ));    X_INV U195 (.IN (\I_1/DCNT [2]), .OUT (n222));    X_AND2 U198 (.IN0 (n223), .IN1 (n173), .OUT (n144));    X_FF \I_0/ZCNT_E_reg  (.IN (\I_0/ZCNT_E638 ), .CLK (n62), .CE (\I_0/n345 ),     .SET (GND), .RST (\I_0/ZCNT_E_reg_GSR_OR ), .OUT (\I_0/ZCNT_E ));    X_INV U199 (.IN (\I_0/ECNT [0]), .OUT (n224));    X_AND2 U201 (.IN0 (n225), .IN1 (n59), .OUT (U201_2_INV));    X_INV U202 (.IN (\I_0/DCNT [2]), .OUT (n226));    X_FF \I_0/ECNT_reg<2>  (.IN (\I_0/ECNT110 [2]), .CLK (n62), .CE     (\I_0/n362 [0]), .SET (GND), .RST (\I_0/ECNT_reg[2]_GSR_OR ), .OUT     (\I_0/ECNT [2]));    X_AND2 U204 (.IN0 (\I_1/DCNT [0]), .IN1 (\I_1/DCNT [2]), .OUT (U204_2_INV));    X_OR2 U205 (.IN0 (\I_1/DCNT [2]), .IN1 (\I_1/DCNT [1]), .OUT (n230));    X_AND2 U206 (.IN0 (n227), .IN1 (\I_1/DCNT [1]), .OUT (U206_2_INV));    X_OR2 U207 (.IN0 (\I_1/DCNT [0]), .IN1 (n227), .OUT (n228));    X_INV U208 (.IN (n439), .OUT (n227));    X_INV U210 (.IN (n233), .OUT (n234));    X_INV U211 (.IN (\I_1/ZCNT_E638 ), .OUT (n232));    X_OR2 U213 (.IN0 (\I_1/CLRZERO ), .IN1 (n234), .OUT (n145));    X_FF \I_1/CLRZERO_reg  (.IN (\I_1/CLRZERO353 ), .CLK (n62), .CE (\I_1/n354 )    , .SET (GND), .RST (\I_1/CLRZERO_reg_GSR_OR ), .OUT (\I_1/CLRZERO ));    X_INV U214 (.IN (\I_1/ECNT_E477 ), .OUT (n235));    X_AND2 U215 (.IN0 (\I_1/n301 ), .IN1 (n235), .OUT (U215_2_INV));    X_OR2 U216 (.IN0 (\I_1/n301 ), .IN1 (\I_1/ECNT_E ), .OUT (n236));    X_INV U218 (.IN (\I_1/EQ2 ), .OUT (n238));    X_OR2 U219 (.IN0 (n439), .IN1 (n238), .OUT (U219_2_INV));    X_FF \I_1/ST_INT_reg  (.IN (\I_1/ST_INT489 ), .CLK (n62), .CE (\I_1/n336 ),     .SET (GND), .RST (\I_1/ST_INT_reg_GSR_OR ), .OUT (n439));    X_INV U220 (.IN (n180), .OUT (n239));    X_INV U221 (.IN (n176), .OUT (n240));    X_INV U223 (.IN (n242), .OUT (n243));    X_INV U224 (.IN (\I_1/ECNT [0]), .OUT (n241));    X_OR2 U226 (.IN0 (n243), .IN1 (n201), .OUT (U226_2_INV));    X_FF \I_1/ECNT_E_reg  (.IN (\I_1/ECNT_E477 ), .CLK (n62), .CE (\I_1/n301 ),     .SET (GND), .RST (\I_1/ECNT_E_reg_GSR_OR ), .OUT (\I_1/ECNT_E ));    X_INV U227 (.IN (\I_0/n301 ), .OUT (n244));    X_OR2 U228 (.IN0 (n244), .IN1 (\I_0/ECNT_E477 ), .OUT (U228_2_INV));    X_OR2 U229 (.IN0 (\I_0/n301 ), .IN1 (\I_0/ECNT_E ), .OUT (U229_2_INV));    X_INV U231 (.IN (n248), .OUT (n249));    X_INV U232 (.IN (\I_0/ZCNT_E638 ), .OUT (n247));    X_OR2 U234 (.IN0 (\I_0/CLRZERO ), .IN1 (n249), .OUT (n141));    X_FF \I_1/ZCNT_E_reg  (.IN (\I_1/ZCNT_E638 ), .CLK (n62), .CE (\I_1/n345 ),     .SET (GND), .RST (\I_1/ZCNT_E_reg_GSR_OR ), .OUT (\I_1/ZCNT_E ));    X_INV U235 (.IN (n438), .OUT (n250));    X_INV U236 (.IN (\I_0/ECNT [4]), .OUT (n251));    X_FF \I_1/DCNT_reg<2>  (.IN (\I_1/DCNT480 [2]), .CLK (n62), .CE     (\I_1/n310 [0]), .SET (GND), .RST (\I_1/DCNT_reg[2]_GSR_OR ), .OUT     (\I_1/DCNT [2]));    X_INV U238 (.IN (n439), .OUT (n252));    X_INV U239 (.IN (n65), .OUT (n253));    X_XOR2 U241 (.IN0 (\I_0/ZCNT [1]), .IN1 (\I_0/ZCNT [0]), .OUT (n254));    X_AND2 U242 (.IN0 (n254), .IN1 (n143), .OUT (n255));    X_FF \I_0/ZCNT_reg<1>  (.IN (n255), .CLK (n62), .CE (\I_0/n370 [0]), .SET     (GND), .RST (\I_0/ZCNT_reg[1]_GSR_OR ), .OUT (\I_0/ZCNT [1]));    X_XOR2 U243 (.IN0 (n256), .IN1 (\I_0/lt_130/AEQB [2]), .OUT (n257));    X_AND2 U244 (.IN0 (\I_0/ZCNT [0]), .IN1 (\I_0/ZCNT [1]), .OUT (n256));    X_AND2 U245 (.IN0 (n257), .IN1 (n143), .OUT (n259));    X_OR2 U246 (.IN0 (\I_0/n104 ), .IN1 (\I_0/E2RQ ), .OUT (n258));    X_FF \I_0/ZCNT_reg<2>  (.IN (n259), .CLK (n62), .CE (\I_0/n370 [0]), .SET     (GND), .RST (\I_0/ZCNT_reg[2]_GSR_OR ), .OUT (\I_0/lt_130/AEQB [2]));    X_XOR2 U248 (.IN0 (n260), .IN1 (\I_0/ECNT [4]), .OUT (n261));    X_AND2 U249 (.IN0 (n171), .IN1 (\I_0/ECNT [3]), .OUT (n260));    X_AND2 U250 (.IN0 (n261), .IN1 (n154), .OUT (\I_0/ECNT110 [4]));    X_XOR2 U251 (.IN0 (n155), .IN1 (\I_0/ECNT [0]), .OUT (n262));    X_AND2 U252 (.IN0 (n262), .IN1 (n154), .OUT (n263));    X_OR2 U253 (.IN0 (\I_0/ECNT [2]), .IN1 (n263), .OUT (n163));    X_FF \I_0/ECNT_reg<4>  (.IN (\I_0/ECNT110 [4]), .CLK (n62), .CE     (\I_0/n362 [0]), .SET (GND), .RST (\I_0/ECNT_reg[4]_GSR_OR ), .OUT     (\I_0/ECNT [4]));    X_XOR2 U254 (.IN0 (\I_0/ECNT [1]), .IN1 (\I_0/ECNT [0]), .OUT (n264));    X_AND2 U255 (.IN0 (n264), .IN1 (n154), .OUT (\I_0/ECNT110 [1]));    X_INV U256 (.IN (n191), .OUT (n265));    X_INV U257 (.IN (n186), .OUT (n266));    X_FF \I_0/ECNT_reg<1>  (.IN (\I_0/ECNT110 [1]), .CLK (n62), .CE