// Xilinx Verilog produced by program ngd2ver, Version M1.4.12// Date: Tue Jan  6 19:10:50 1998// Design file: time_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd  module ff_example (RESET, CLOCK, ENABLE, D_IN, A_Q_OUT, B_Q_OUT, C_Q_OUT,   D_Q_OUT);    input RESET;    input CLOCK;    input ENABLE;    input [7:0] D_IN;    output [7:0] A_Q_OUT;    output [7:0] B_Q_OUT;    output [7:0] C_Q_OUT;    output [7:0] D_Q_OUT;    wire n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n478    , n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,     n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,     \D_Q_OUT_reg[6]_GSR_OR , \D_Q_OUT_reg[7]_GSR_OR , \D_Q_OUT_reg[4]_GSR_OR ,     \D_Q_OUT_reg[5]_GSR_OR , \D_Q_OUT_reg[2]_GSR_OR , \D_Q_OUT_reg[3]_GSR_OR ,     \D_Q_OUT_reg[0]_GSR_OR , \D_Q_OUT_reg[1]_GSR_OR ,     \A_Q_OUT_reg[7]/$1I11/QINT , \A_Q_OUT_reg[7]/$1I11/OBUF_GTS_TRI ,     \A_Q_OUT_reg[6]/$1I11/QINT , \A_Q_OUT_reg[6]/$1I11/OBUF_GTS_TRI ,     \A_Q_OUT_reg[5]/$1I11/QINT , \A_Q_OUT_reg[5]/$1I11/OBUF_GTS_TRI ,     \A_Q_OUT_reg[4]/$1I11/QINT , \A_Q_OUT_reg[4]/$1I11/OBUF_GTS_TRI ,     \A_Q_OUT_reg[3]/$1I11/QINT , \A_Q_OUT_reg[3]/$1I11/OBUF_GTS_TRI ,     \A_Q_OUT_reg[2]/$1I11/QINT , \A_Q_OUT_reg[2]/$1I11/OBUF_GTS_TRI ,     \A_Q_OUT_reg[1]/$1I11/QINT , \A_Q_OUT_reg[1]/$1I11/OBUF_GTS_TRI ,     \A_Q_OUT_reg[0]/$1I11/QINT , \A_Q_OUT_reg[0]/$1I11/OBUF_GTS_TRI ,     \U272/$1I20_GTS_TRI , \U273/$1I20_GTS_TRI , \U274/$1I20_GTS_TRI ,     \U275/$1I20_GTS_TRI , \U276/$1I20_GTS_TRI , \U277/$1I20_GTS_TRI ,     \U278/$1I20_GTS_TRI , \U279/$1I20_GTS_TRI , \U280/$1I20_GTS_TRI ,     \U281/$1I20_GTS_TRI , \U282/$1I20_GTS_TRI , \U283/$1I20_GTS_TRI ,     \U284/$1I20_GTS_TRI , \U285/$1I20_GTS_TRI , \U286/$1I20_GTS_TRI ,     \U287/$1I20_GTS_TRI , \U288/$1I20_GTS_TRI , \U289/$1I20_GTS_TRI ,     \U290/$1I20_GTS_TRI , \U291/$1I20_GTS_TRI , \U292/$1I20_GTS_TRI ,     \U293/$1I20_GTS_TRI , \U294/$1I20_GTS_TRI , \U295/$1I20_GTS_TRI ,     \B_Q_OUT_reg[6]/$1I13_GSR_OR , \B_Q_OUT_reg[7]/$1I13_GSR_OR ,     \B_Q_OUT_reg[4]/$1I13_GSR_OR , \B_Q_OUT_reg[5]/$1I13_GSR_OR ,     \B_Q_OUT_reg[2]/$1I13_GSR_OR , \B_Q_OUT_reg[3]/$1I13_GSR_OR ,     \B_Q_OUT_reg[0]/$1I13_GSR_OR , \B_Q_OUT_reg[1]/$1I13_GSR_OR ,     \C_Q_OUT_reg[6]/$1I13_GSR_OR , \C_Q_OUT_reg[7]/$1I13_GSR_OR ,     \C_Q_OUT_reg[4]/$1I13_GSR_OR , \C_Q_OUT_reg[5]/$1I13_GSR_OR ,     \C_Q_OUT_reg[2]/$1I13_GSR_OR , \C_Q_OUT_reg[3]/$1I13_GSR_OR ,     \C_Q_OUT_reg[0]/$1I13_GSR_OR , \C_Q_OUT_reg[1]/$1I13_GSR_OR ,     \U262/clkio_bufsig , \A_Q_OUT_reg[7]/$1I11/OBUF_GTS_TRI_2_INV ,     \A_Q_OUT_reg[6]/$1I11/OBUF_GTS_TRI_2_INV ,     \A_Q_OUT_reg[5]/$1I11/OBUF_GTS_TRI_2_INV ,     \A_Q_OUT_reg[4]/$1I11/OBUF_GTS_TRI_2_INV ,     \A_Q_OUT_reg[3]/$1I11/OBUF_GTS_TRI_2_INV ,     \A_Q_OUT_reg[2]/$1I11/OBUF_GTS_TRI_2_INV ,     \A_Q_OUT_reg[1]/$1I11/OBUF_GTS_TRI_2_INV ,     \A_Q_OUT_reg[0]/$1I11/OBUF_GTS_TRI_2_INV , \U272/$1I20_GTS_TRI_2_INV ,     \U273/$1I20_GTS_TRI_2_INV , \U274/$1I20_GTS_TRI_2_INV ,     \U275/$1I20_GTS_TRI_2_INV , \U276/$1I20_GTS_TRI_2_INV ,     \U277/$1I20_GTS_TRI_2_INV , \U278/$1I20_GTS_TRI_2_INV ,     \U279/$1I20_GTS_TRI_2_INV , \U280/$1I20_GTS_TRI_2_INV ,     \U281/$1I20_GTS_TRI_2_INV , \U282/$1I20_GTS_TRI_2_INV ,     \U283/$1I20_GTS_TRI_2_INV , \U284/$1I20_GTS_TRI_2_INV ,     \U285/$1I20_GTS_TRI_2_INV , \U286/$1I20_GTS_TRI_2_INV ,     \U287/$1I20_GTS_TRI_2_INV , \U288/$1I20_GTS_TRI_2_INV ,     \U289/$1I20_GTS_TRI_2_INV , \U290/$1I20_GTS_TRI_2_INV ,     \U291/$1I20_GTS_TRI_2_INV , \U292/$1I20_GTS_TRI_2_INV ,     \U293/$1I20_GTS_TRI_2_INV , \U294/$1I20_GTS_TRI_2_INV ,     \U295/$1I20_GTS_TRI_2_INV , GND, VCC;    `ifdef GSR_SIGNAL      wire GSR = `GSR_SIGNAL ;    `else      wire GSR ;    `endif    `ifdef GTS_SIGNAL      wire GTS = `GTS_SIGNAL ;    `else      wire GTS ;    `endif    initial $sdf_annotate("time_sim.sdf");    X_BUF U261 (.IN (RESET), .OUT (n263));    X_BUF U263 (.IN (ENABLE), .OUT (n265));    X_BUF U264 (.IN (D_IN[7]), .OUT (n266));    X_BUF U265 (.IN (D_IN[6]), .OUT (n267));    X_BUF U266 (.IN (D_IN[5]), .OUT (n268));    X_BUF U267 (.IN (D_IN[4]), .OUT (n269));    X_BUF U268 (.IN (D_IN[3]), .OUT (n270));    X_BUF U269 (.IN (D_IN[2]), .OUT (n271));    X_BUF U270 (.IN (D_IN[1]), .OUT (n272));    X_BUF U271 (.IN (D_IN[0]), .OUT (n273));    X_FF \D_Q_OUT_reg<6>  (.IN (n267), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[6]_GSR_OR ), .OUT (n495));    X_FF \D_Q_OUT_reg<7>  (.IN (n266), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[7]_GSR_OR ), .OUT (n494));    X_FF \D_Q_OUT_reg<4>  (.IN (n269), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[4]_GSR_OR ), .OUT (n497));    X_FF \D_Q_OUT_reg<5>  (.IN (n268), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[5]_GSR_OR ), .OUT (n496));    X_FF \D_Q_OUT_reg<2>  (.IN (n271), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[2]_GSR_OR ), .OUT (n499));    X_FF \D_Q_OUT_reg<3>  (.IN (n270), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[3]_GSR_OR ), .OUT (n498));    X_FF \D_Q_OUT_reg<0>  (.IN (n273), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[0]_GSR_OR ), .OUT (n501));    X_FF \D_Q_OUT_reg<1>  (.IN (n272), .CLK (n264), .CE (n265), .SET (GND),     .RST (\D_Q_OUT_reg[1]_GSR_OR ), .OUT (n500));    X_IPAD RESET_PAD (.PAD (RESET));    X_IPAD CLOCK_PAD (.PAD (CLOCK));    X_IPAD ENABLE_PAD (.PAD (ENABLE));    X_IPAD \D_IN<7>_PAD  (.PAD (D_IN[7]));    X_IPAD \D_IN<6>_PAD  (.PAD (D_IN[6]));    X_IPAD \D_IN<5>_PAD  (.PAD (D_IN[5]));    X_IPAD \D_IN<4>_PAD  (.PAD (D_IN[4]));    X_IPAD \D_IN<3>_PAD  (.PAD (D_IN[3]));    X_IPAD \D_IN<2>_PAD  (.PAD (D_IN[2]));    X_IPAD \D_IN<1>_PAD  (.PAD (D_IN[1]));    X_IPAD \D_IN<0>_PAD  (.PAD (D_IN[0]));    X_OPAD \A_Q_OUT<7>_PAD  (.PAD (A_Q_OUT[7]));    X_OPAD \A_Q_OUT<6>_PAD  (.PAD (A_Q_OUT[6]));    X_OPAD \A_Q_OUT<5>_PAD  (.PAD (A_Q_OUT[5]));    X_OPAD \A_Q_OUT<4>_PAD  (.PAD (A_Q_OUT[4]));    X_OPAD \A_Q_OUT<3>_PAD  (.PAD (A_Q_OUT[3]));    X_OPAD \A_Q_OUT<2>_PAD  (.PAD (A_Q_OUT[2]));    X_OPAD \A_Q_OUT<1>_PAD  (.PAD (A_Q_OUT[1]));    X_OPAD \A_Q_OUT<0>_PAD  (.PAD (A_Q_OUT[0]));    X_OPAD \B_Q_OUT<7>_PAD  (.PAD (B_Q_OUT[7]));    X_OPAD \B_Q_OUT<6>_PAD  (.PAD (B_Q_OUT[6]));    X_OPAD \B_Q_OUT<5>_PAD  (.PAD (B_Q_OUT[5]));    X_OPAD \B_Q_OUT<4>_PAD  (.PAD (B_Q_OUT[4]));    X_OPAD \B_Q_OUT<3>_PAD  (.PAD (B_Q_OUT[3]));    X_OPAD \B_Q_OUT<2>_PAD  (.PAD (B_Q_OUT[2]));    X_OPAD \B_Q_OUT<1>_PAD  (.PAD (B_Q_OUT[1]));    X_OPAD \B_Q_OUT<0>_PAD  (.PAD (B_Q_OUT[0]));    X_OPAD \C_Q_OUT<7>_PAD  (.PAD (C_Q_OUT[7]));    X_OPAD \C_Q_OUT<6>_PAD  (.PAD (C_Q_OUT[6]));    X_OPAD \C_Q_OUT<5>_PAD  (.PAD (C_Q_OUT[5]));    X_OPAD \C_Q_OUT<4>_PAD  (.PAD (C_Q_OUT[4]));    X_OPAD \C_Q_OUT<3>_PAD  (.PAD (C_Q_OUT[3]));    X_OPAD \C_Q_OUT<2>_PAD  (.PAD (C_Q_OUT[2]));    X_OPAD \C_Q_OUT<1>_PAD  (.PAD (C_Q_OUT[1]));    X_OPAD \C_Q_OUT<0>_PAD  (.PAD (C_Q_OUT[0]));    X_OPAD \D_Q_OUT<7>_PAD  (.PAD (D_Q_OUT[7]));    X_OPAD \D_Q_OUT<6>_PAD  (.PAD (D_Q_OUT[6]));    X_OPAD \D_Q_OUT<5>_PAD  (.PAD (D_Q_OUT[5]));    X_OPAD \D_Q_OUT<4>_PAD  (.PAD (D_Q_OUT[4]));    X_OPAD \D_Q_OUT<3>_PAD  (.PAD (D_Q_OUT[3]));    X_OPAD \D_Q_OUT<2>_PAD  (.PAD (D_Q_OUT[2]));    X_OPAD \D_Q_OUT<1>_PAD  (.PAD (D_Q_OUT[1]));    X_OPAD \D_Q_OUT<0>_PAD  (.PAD (D_Q_OUT[0]));    X_OR2 \D_Q_OUT_reg<6>_GSR_OR_201  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[6]_GSR_OR ));    X_OR2 \D_Q_OUT_reg<7>_GSR_OR_202  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[7]_GSR_OR ));    X_OR2 \D_Q_OUT_reg<4>_GSR_OR_203  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[4]_GSR_OR ));    X_OR2 \D_Q_OUT_reg<5>_GSR_OR_204  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[5]_GSR_OR ));    X_OR2 \D_Q_OUT_reg<2>_GSR_OR_205  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[2]_GSR_OR ));    X_OR2 \D_Q_OUT_reg<3>_GSR_OR_206  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[3]_GSR_OR ));    X_OR2 \D_Q_OUT_reg<0>_GSR_OR_207  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[0]_GSR_OR ));    X_OR2 \D_Q_OUT_reg<1>_GSR_OR_208  (.IN0 (n263), .IN1 (GSR), .OUT     (\D_Q_OUT_reg[1]_GSR_OR ));    X_FF \A_Q_OUT_reg<7>/$1I11/FF  (.IN (n266), .CLK (n264), .CE (VCC), .SET     (GND), .RST (GSR), .OUT (\A_Q_OUT_reg[7]/$1I11/QINT ));    X_BUF \A_Q_OUT_reg<7>/$1I11/OBUF  (.IN (\A_Q_OUT_reg[7]/$1I11/QINT ), .OUT     (\A_Q_OUT_reg[7]/$1I11/OBUF_GTS_TRI ));    X_TRI \A_Q_OUT_reg<7>/$1I11/OBUF_GTS_TRI_209  (.IN     (\A_Q_OUT_reg[7]/$1I11/OBUF_GTS_TRI ), .OUT (A_Q_OUT[7]), .CTL     (\A_Q_OUT_reg[7]/$1I11/OBUF_GTS_TRI_2_INV ));    X_FF \A_Q_OUT_reg<6>/$1I11/FF  (.IN (n267), .CLK (n264), .CE (VCC), .SET     (GND), .RST (GSR), .OUT (\A_Q_OUT_reg[6]/$1I11/QINT ));    X_BUF \A_Q_OUT_reg<6>/$1I11/OBUF  (.IN (\A_Q_OUT_reg[6]/$1I11/QINT ), .OUT     (\A_Q_OUT_reg[6]/$1I11/OBUF_GTS_TRI ));    X_TRI \A_Q_OUT_reg<6>/$1I11/OBUF_GTS_TRI_210  (.IN     (\A_Q_OUT_reg[6]/$1I11/OBUF_GTS_TRI ), .OUT (A_Q_OUT[6]), .CTL     (\A_Q_OUT_reg[6]/$1I11/OBUF_GTS_TRI_2_INV ));    X_FF \A_Q_OUT_reg<5>/$1I11/FF  (.IN (n268), .CLK (n264), .CE (VCC), .SET     (GND), .RST (GSR), .OUT (\A_Q_OUT_reg[5]/$1I11/QINT ));    X_BUF \A_Q_OUT_reg<5>/$1I11/OBUF  (.IN (\A_Q_OUT_reg[5]/$1I11/QINT ), .OUT     (\A_Q_OUT_reg[5]/$1I11/OBUF_GTS_TRI ));    X_TRI \A_Q_OUT_reg<5>/$1I11/OBUF_GTS_TRI_211  (.IN     (\A_Q_OUT_reg[5]/$1I11/OBUF_GTS_TRI ), .OUT (A_Q_OUT[5]), .CTL     (\A_Q_OUT_reg[5]/$1I11/OBUF_GTS_TRI_2_INV ));    X_FF \A_Q_OUT_reg<4>/$1I11/FF  (.IN (n269), .CLK (n264), .CE (VCC), .SET     (GND), .RST (GSR), .OUT (\A_Q_OUT_reg[4]/$1I11/QINT ));    X_BUF \A_Q_OUT_reg<4>/$1I11/OBUF  (.IN (\A_Q_OUT_reg[4]/$1I11/QINT ), .OUT     (\A_Q_OUT_reg[4]/$1I11/OBUF_GTS_TRI ));    X_TRI \A_Q_OUT_reg<4>/$1I11/OBUF_GTS_TRI_212  (.IN     (\A_Q_OUT_reg[4]/$1I11/OBUF_GTS_TRI ), .OUT (A_Q_OUT[4]), .CTL     (\A_Q_OUT_reg[4]/$1I11/OBUF_GTS_TRI_2_INV ));    X_FF \A_Q_OUT_reg<3>/$1I11/FF  (.IN (n270), .CLK (n264), .CE (VCC), .SET     (GND), .RST (GSR), .OUT (\A_Q_OUT_reg[3]/$1I11/QINT ));    X_BUF \A_Q_OUT_reg<3>/$1I11/OBUF  (.IN (\A_Q_OUT_reg[3]/$1I11/QINT ), .OUT     (\A_Q_OUT_reg[3]/$1I11/OBUF_GTS_TRI ));    X_TRI \A_Q_OUT_reg<3>/$1I11/OBUF_GTS_TRI_213  (.IN     (\A_Q_OUT_reg[3]/$1I11/OBUF_GTS_TRI ), .OUT (A_Q_OUT[3]), .CTL     (\A_Q_OUT_reg[3]/$1I11/OBUF_GTS_TRI_2_INV ));    X_FF \A_Q_OUT_reg<2>/$1I11/FF  (.IN (n271), .CLK (n264), .CE (VCC), .SET     (GND), .RST (GSR), .OUT (\A_Q_OUT_reg[2]/$1I11/QINT ));    X_BUF \A_Q_OUT_reg<2>/$1I11/OBUF  (.IN (\A_Q_OUT_reg[2]/$1I11/QINT ), .OUT     (\A_Q_OUT_reg[2]/$1I11/OBUF_GTS_TRI ));    X_TRI \A_Q_OUT_reg<2>/$1I11/OBUF_GTS_TRI_214  (.IN     (\A_Q_OUT_reg[2]/$1I11/OBUF_GTS_TRI ), .OUT (A_Q_OUT[2]), .CTL     (\A_Q_OUT_reg[2]/$1I11/OBUF_GTS_TRI_2_INV ));    X_FF \A_Q_OUT_reg<1>/$1I11/FF  (.IN (n272), .CLK (n264), .CE (VCC), .SET     (GND), .RST (GSR), .OUT (\A_Q_OUT_reg[1]/$1I11/QINT ));    X_BUF \A_Q_OUT_reg<1>/$1I11/OBUF  (.IN (\A_Q_OUT_reg[1]/$1I11/QINT ), .OUT     (\A_Q_OUT_reg[1]/$1I11/OBUF_GTS_TRI ));    X_TRI \A_Q_OUT_reg<1>/$1I11/OBUF_GTS_TRI_215  (.IN     (\A_Q_OUT_reg[1]/$1I11/OBUF_GTS_TRI ), .OUT (A_Q_OUT[1]), .CTL     (\A_Q_OUT_reg[1]/$1I11/OBUF_GTS_TRI_2_INV ));    X_FF \A_Q_OUT_reg<0>/$1I11/FF  (.IN (n273), .CLK (n264), .CE (VCC), .SET