?? m500auc.lst
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C51 COMPILER V7.10 M500AUC 11/18/2004 15:28:02 PAGE 1
C51 COMPILER V7.10, COMPILATION OF MODULE M500AUC
OBJECT MODULE PLACED IN M500AuC.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE M500AuC.c LARGE WARNINGLEVEL(0) BROWSE INCDIR(D:\UsefulDocument\Mifare\MF R
-C500\MFRC500 Demo Reader\RC500\For Test) DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMBOLS
line level source
1 ///////////////////////////////////////////////////////////////////////////////
2 // Copyright (c), Philips Semiconductors Gratkorn
3 //
4 // (C)PHILIPS Electronics N.V.2000
5 // All rights are reserved. Reproduction in whole or in part is
6 // prohibited without the written consent of the copyright owner.
7 // Philips reserves the right to make changes without notice at any time.
8 // Philips makes no warranty, expressed, implied or statutory, including but
9 // not limited to any implied warranty of merchantibility or fitness for any
10 //particular purpose, or that the use will not infringe any third party patent,
11 // copyright or trademark. Philips must not be liable for any loss or damage
12 // arising from its use.
13 ///////////////////////////////////////////////////////////////////////////////
14 #define DLL_EXPORT // library source module definition
15 #include <p89c51rx.h>
1 =1 /*--------------------------------------------------------------------------
2 =1 P89C51.H
3 =1
4 =1 Header file for the ISP Flash Philips P89C51RX.
5 =1 --------------------------------------------------------------------------*/
6 =1
7 =1 /*------------------------------------------------
8 =1 Byte Registers
9 =1 ------------------------------------------------*/
10 =1 sfr P0 = 0x80;
11 =1 sfr SP = 0x81;
12 =1 sfr DPL = 0x82;
13 =1 sfr DPH = 0x83;
14 =1 sfr PCON = 0x87;
15 =1 sfr TCON = 0x88;
16 =1 sfr TMOD = 0x89;
17 =1 sfr TL0 = 0x8A;
18 =1 sfr TL1 = 0x8B;
19 =1 sfr TH0 = 0x8C;
20 =1 sfr TH1 = 0x8D;
21 =1 sfr AUXR = 0x8E;
22 =1 sfr P1 = 0x90;
23 =1 sfr SCON = 0x98;
24 =1 sfr SBUF = 0x99;
25 =1 sfr P2 = 0xA0;
26 =1 sfr AUXR1 = 0xA2;
27 =1 sfr IE = 0xA8;
28 =1 sfr SADDR = 0xA9;
29 =1 sfr P3 = 0xB0;
30 =1 sfr IPH = 0xB7;
31 =1 sfr IP = 0xB8;
32 =1 sfr SADEN = 0xB9;
33 =1 sfr PMR = 0xC4;
34 =1 sfr T2CON = 0xC8;
35 =1 sfr T2MOD = 0xC9;
36 =1 sfr RCAP2L = 0xCA;
37 =1 sfr RCAP2H = 0xCB;
38 =1 sfr TL2 = 0xCC;
39 =1 sfr TH2 = 0xCD;
C51 COMPILER V7.10 M500AUC 11/18/2004 15:28:02 PAGE 2
40 =1 sfr PSW = 0xD0;
41 =1 sfr CCON = 0xD8;
42 =1 sfr CMOD = 0xD9;
43 =1 sfr CCAPM0 = 0xDA;
44 =1 sfr CCAPM1 = 0xDB;
45 =1 sfr CCAPM2 = 0xDC;
46 =1 sfr CCAPM3 = 0xDD;
47 =1 sfr CCAPM4 = 0xDE;
48 =1 sfr ACC = 0xE0;
49 =1 sfr A = 0xE0;
50 =1 sfr CL = 0xE9;
51 =1 sfr CCAP0L = 0xEA;
52 =1 sfr CCAP1L = 0xEB;
53 =1 sfr CCAP2L = 0xEC;
54 =1 sfr CCAP3L = 0xED;
55 =1 sfr CCAP4L = 0xEE;
56 =1 sfr B = 0xF0;
57 =1 sfr CH = 0xF9;
58 =1 sfr CCAP0H = 0xFA;
59 =1 sfr CCAP1H = 0xFB;
60 =1 sfr CCAP2H = 0xFC;
61 =1 sfr CCAP3H = 0xFD;
62 =1 sfr CCAP4H = 0xFE;
63 =1
64 =1 /*------------------------------------------------
65 =1 P0 Bit Registers
66 =1 ------------------------------------------------*/
67 =1 sbit P0_0 = 0x80;
68 =1 sbit P0_1 = 0x81;
69 =1 sbit P0_2 = 0x82;
70 =1 sbit P0_3 = 0x83;
71 =1 sbit P0_4 = 0x84;
72 =1 sbit P0_5 = 0x85;
73 =1 sbit P0_6 = 0x86;
74 =1 sbit P0_7 = 0x87;
75 =1
76 =1 /*------------------------------------------------
77 =1 PCON Bit Values
78 =1 ------------------------------------------------*/
79 =1 #define IDL_ 0x01
80 =1
81 =1 #define STOP_ 0x02
82 =1 #define PD_ 0x02 /* Alternate definition */
83 =1
84 =1 #define GF0_ 0x04
85 =1 #define GF1_ 0x08
86 =1
87 =1 #define SMOD_ 0x80
88 =1
89 =1 /*------------------------------------------------
90 =1 TCON Bit Registers
91 =1 ------------------------------------------------*/
92 =1 sbit IT0 = 0x88;
93 =1 sbit IE0 = 0x89;
94 =1 sbit IT1 = 0x8A;
95 =1 sbit IE1 = 0x8B;
96 =1 sbit TR0 = 0x8C;
97 =1 sbit TF0 = 0x8D;
98 =1 sbit TR1 = 0x8E;
99 =1 sbit TF1 = 0x8F;
100 =1
101 =1 /*------------------------------------------------
C51 COMPILER V7.10 M500AUC 11/18/2004 15:28:02 PAGE 3
102 =1 T2CON Bit Registers
103 =1 ------------------------------------------------*/
104 =1 sbit TF2 = 0xCF;
105 =1 sbit EXF2 = 0xCE;
106 =1 sbit RCLK = 0xCD;
107 =1 sbit TCLK = 0xCC;
108 =1 sbit EXEN2 = 0xCB;
109 =1 sbit TR2 = 0xCA;
110 =1 sbit C_T2 = 0xC9;
111 =1 sbit CP_RL2= 0xC8;
112 =1
113 =1 /*------------------------------------------------
114 =1 TMOD Bit Values
115 =1 ------------------------------------------------*/
116 =1 #define T0_M0_ 0x01
117 =1 #define T0_M1_ 0x02
118 =1 #define T0_CT_ 0x04
119 =1 #define T0_GATE_ 0x08
120 =1 #define T1_M0_ 0x10
121 =1 #define T1_M1_ 0x20
122 =1 #define T1_CT_ 0x40
123 =1 #define T1_GATE_ 0x80
124 =1
125 =1 #define T1_MASK_ 0xF0
126 =1 #define T0_MASK_ 0x0F
127 =1
128 =1 /*------------------------------------------------
129 =1 P1 Bit Registers
130 =1 ------------------------------------------------*/
131 =1 sbit P1_0 = 0x90;
132 =1 sbit P1_1 = 0x91;
133 =1 sbit P1_2 = 0x92;
134 =1 sbit P1_3 = 0x93;
135 =1 sbit P1_4 = 0x94;
136 =1 sbit P1_5 = 0x95;
137 =1 sbit P1_6 = 0x96;
138 =1 sbit P1_7 = 0x97;
139 =1
140 =1 /*------------------------------------------------
141 =1 SCON Bit Registers
142 =1 ------------------------------------------------*/
143 =1 sbit RI = 0x98;
144 =1 sbit TI = 0x99;
145 =1 sbit RB8 = 0x9A;
146 =1 sbit TB8 = 0x9B;
147 =1 sbit REN = 0x9C;
148 =1 sbit SM2 = 0x9D;
149 =1 sbit SM1 = 0x9E;
150 =1 sbit SM0 = 0x9F;
151 =1
152 =1 /*------------------------------------------------
153 =1 P2 Bit Registers
154 =1 ------------------------------------------------*/
155 =1 sbit P2_0 = 0xA0;
156 =1 sbit P2_1 = 0xA1;
157 =1 sbit P2_2 = 0xA2;
158 =1 sbit P2_3 = 0xA3;
159 =1 sbit P2_4 = 0xA4;
160 =1 sbit P2_5 = 0xA5;
161 =1 sbit P2_6 = 0xA6;
162 =1 sbit P2_7 = 0xA7;
163 =1
C51 COMPILER V7.10 M500AUC 11/18/2004 15:28:02 PAGE 4
164 =1 /*------------------------------------------------
165 =1 IE Bit Registers
166 =1 ------------------------------------------------*/
167 =1 sbit EX0 = 0xA8; /* 1=Enable External interrupt 0 */
168 =1 sbit ET0 = 0xA9; /* 1=Enable Timer 0 interrupt */
169 =1 sbit EX1 = 0xAA; /* 1=Enable External interrupt 1 */
170 =1 sbit ET1 = 0xAB; /* 1=Enable Timer 1 interrupt */
171 =1 sbit ES = 0xAC; /* 1=Enable Serial port interrupt */
172 =1 sbit ET2 = 0xAD; /* 1=Enable Timer 2 interrupt */
173 =1 sbit EC = 0XAE; /* 1=Enable PCA interrupt */
174 =1 sbit EA = 0xAF; /* 0=Disable all interrupts */
175 =1
176 =1 /*------------------------------------------------
177 =1 P3 Bit Registers (Mnemonics & Ports)
178 =1 ------------------------------------------------*/
179 =1 sbit P3_0 = 0xB0;
180 =1 sbit P3_1 = 0xB1;
181 =1 sbit P3_2 = 0xB2;
182 =1 sbit P3_3 = 0xB3;
183 =1 sbit P3_4 = 0xB4;
184 =1 sbit P3_5 = 0xB5;
185 =1 sbit P3_6 = 0xB6;
186 =1 sbit P3_7 = 0xB7;
187 =1
188 =1 sbit RXD = 0xB0; /* Serial data input */
189 =1 sbit TXD = 0xB1; /* Serial data output */
190 =1 sbit INT0 = 0xB2; /* External interrupt 0 */
191 =1 sbit INT1 = 0xB3; /* External interrupt 1 */
192 =1 sbit T0 = 0xB4; /* Timer 0 external input */
193 =1 sbit T1 = 0xB5; /* Timer 1 external input */
194 =1 sbit WR = 0xB6; /* External data memory write strobe */
195 =1 sbit RD = 0xB7; /* External data memory read strobe */
196 =1
197 =1 /*------------------------------------------------
198 =1 IP Bit Registers
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