/* MII register (8129 only) */
/* Offset 005Ah - R/W */

#define RTL_MII_CLK			0x01
#define RTL_MII_DATAIN		0x02
#define RTL_MII_DATAOUT		0x04
#define RTL_MII_DIR			0x80	/* 0 == input, 1 == output */

/*
 * EEPROM control register
 */

#define RTL_EE_DATAOUT			0x01		/* Data out */
#define RTL_EE_DATAIN			0x02		/* Data in */
#define RTL_EE_CLK				0x04		/* clock */
#define RTL_EE_SEL				0x08		/* chip select */
#define RTL_EE_MODE				(0x40|0x80)

/* 9346 EEPROM commands */
#define RTL_EECMD_WRITE			0x140
#define RTL_EECMD_READ			0x180
#define RTL_EECMD_ERASE			0x1c0

#define RTL_EE_ID				0x00
#define RTL_EE_PCI_VID			0x01
#define RTL_EE_PCI_DID			0x02

/* Location of station address inside EEPROM */
#define RTL_EE_EADDR			0x07




/* Configuration Register 0 */
/* Offset 0051h - R/W */

#define RTL_CONFIG0_BS2			0x04		/* Boot ROM Size */
#define RTL_CONFIG0_BS1			0x02		/* 000 - No  Boot Rom */
#define RTL_CONFIG0_BS0			0x01		/* 001 - 8k  Boot Rom */
											/* 010 - 16k Boot Rom */
											/* 011 - 32k Boot Rom */
											/* 100 - 64k Boot Rom */
											/* 101 - 128 Boot Rom */
											/* 110 - unused */
											/* 111 - unused */

/* Configuration Register 1 */
/* Offset 0052h - R/W */

#define RTL_CONFIG1_LEDS1		0x80		/* LED's */
#define RTL_CONFIG1_LEDS0		0x40		/* Refer to LED IFace */
#define RTL_CONFIG1_DVRLOAD		0x20		/* Driver loaded status bit */
#define RTL_CONFIG1_LWACT		0x10		/* LWAKE Active mode */
#define RTL_CONFIG1_MEMMAP		0x08		/* Registers Mapped to PCI Memory */
#define RTL_CONFIG1_IOMAP		0x04		/* Registers Mapped to PCI I/O space */
#define RTL_CONFIG1_VPD			0x02		/* Vital Product Data */
#define RTL_CONFIG1_PMEN		0x01		/* Power Management Enable */

/* Media Status Bits 	*/
/* Offset 0058h - R/W 	*/

#define RTL_MED_RXPF				0x01	/* Rx Pause Flag */
#define RTL_MED_TXPF				0x02	/* Tx Pause Flag */
#define	RTL_MED_LINKB				0x04	/* Inverse of Link Status */
											/* 0 - Link OK */
#define	RTL_MED_SPEED				0x08    /* 1 - 10Mbps, 0 - 100Mbps */
#define RTL_MED_AUX					0x10	/* Aux power Status */
#define	RTL_MED_RXFCE				0x40	/* Rx Flow Control enable */
#define	RTL_MED_TXFCE				0x80	/* Tx Flow control enable */

/* Configuration Register 3	*/
/* Offset 0059h - R/W 		*/

#define RTL_CONFIG3_GNTSEL			0x80	/* Grant Select */
#define RTL_CONFIG3_PARM_EN			0x40	/* Paramater Enable - 100Mbps only */
#define RTL_CONFIG3_MAGIC			0x20	/* Magic Packet */
#define RTL_CONFIG3_LINKUP			0x10
#define RTL_CONFIG3_CARDB_EN		0x08	/* Card Bus Enable */
#define RTL_CONFIG3_CLKRUN_EN		0x04
#define RTL_CONFIG3_FUNCREG_EN		0x02	/* Functions registers enable */
#define RTL_CONFIG3_FBTBEN			0x01	/* Fast back to back enable */

/* Configuration Register 4 */
/* Offset 005Ah - R/W 		*/

#define RTL_CONFIG4_RXFIFO_CLR		0x80	/* Automatically clear RX FIFO OFlow */
#define RTL_CONFIG4_ANAOFF			0x40	/* Analogue Power Off */
#define RTL_CONFIG4_LONGWF			0x20	/* Long Wake up Frame */
#define RTL_CONFIG4_LWPME			0x10	/* LANWAKE vs PMEB */
#define RTL_CONFIG4_MSWFB			0x08	/* Microsoft Wake up frame */
#define RTL_CONFIG4_LWPTN			0x04	/* LWAKE Pattern */
#define RTL_CONFIG4_PARM_EN2		0x02	/* Parameter Enable 2  */
#define RTL_CONFIG4_RD_AUX			0x01	/* Rev d - Aux Power Status */


/* Transmit Status of all Descriptors */
/* Offset 0060 - 0061h - R/W 		  */
/* RTL_REGS_TX_SUMMARY			      */

#define RTL_TSAD_TOK_MSK			0xf000	/* Tx Ok Descs          */
#define RTL_TSAD_TUN_MSK			0x0f00	/* Tx Underrun Descs    */
#define RTL_TSAD_TABT_MSK			0x00f0	/* Transmit Abort Descs */
#define RTL_TSAD_OWN_MSK			0x000f	/* OWN Bit Descriptors  */

/* Basic Mode Control Register 	*/
/* Offset 0062-0063h - R/W 		*/
/* Note : All Default are 0 	*/

#define	RTL_BMCR_RESET				0x8000	/* Sets Status and Control Regs */
											/* 1=Software reset 0=normal op */

#define	RTL_BMCR_SPD_SET			0x2000	/* Network Speed */
											/* 1=100Mbps, 0=10Mbps */

#define	RTL_BMCR_ANE				0x1000	/* Auto Negotiation Enable */
#define	RTL_BMCR_RAN				0x0200	/* Restart Auto Negotiation */
#define	RTL_BMCR_DUPX				0x0100	/* Duplex mode */
											/* 1=full duplex, 0=normal */
/* Basic Mode Status Register 	*/
/* Offset 0064-0065h - R/W 		*/

#define	RTL_BMSR_100BASE_T4			0x8000	/* 1=enable, default = 0 */
#define	RTL_BMSR_100BASE_TX_FDUPX	0x4000	/* 1=enable, default = 1 */
#define	RTL_BMSR_100BASE_TX_HDUPX	0x2000	/* 1=enable, default = 1 */
#define	RTL_BMSR_10BASE_T_FDUPX		0x1000	/* 1=enable, default = 1 */
#define	RTL_BMSR_10BASE_T_HDUPX		0x0800	/* 1=enable, default = 1 */

#define	RTL_BMSR_AUTO_NEG_COMP		0x0020	/* 1=completed,   default = 0 */
#define	RTL_BMSR_REMOTE_FAULT		0x0010	/* 1=detected,    default = 0 */
#define	RTL_BMSR_AUTO_NEG_FAIL		0x0008	/* 1=failed,      default = 1 */
#define	RTL_BMSR_LINK_STATUS		0x0004	/* 1=established, default = 0 */
#define	RTL_BMSR_JABBER_DETECT		0x0002	/* 1=detected,    default = 0 */
#define	RTL_BMSR_EXT_CAPABILITY		0x0001	/* 1=extended,    default = 1 */
											/* 0=basic regs */

/* Auto Negotiation Advertisement Register 	*/
/* Offset 0066-0067h - R/W 		*/

#define	RTL_ANAR_NP			0x8000	/* Next Page Bit */
									/* 0=primary capability data page 	*/
									/* 1=protocol specific data page	*/
									/* default = 0 */

#define	RTL_ANAR_ACK		0x4000	/* 1=acknowledge, default = 0 */

#define	RTL_ANAR_RF			0x2000	/* 1=advertise remote fault detection	*/
									/*  default = 0 */

#define	RTL_ANAR_PAUSE		0x0400	/* 1=flow control supported locally */
									/* default comes from EEPROM */

#define	RTL_ANAR_T4			0x0200	/* 1=100Base-T4 supported */
									/* default = 0 */

#define	RTL_ANAR_TXFD		0x0100	/* 1=100Base-Tx full duplex supported */
									/* default = 1 */

#define	RTL_ANAR_TX			0x0080	/* 1=100Base-Tx supported */
									/* default = 1 */

#define	RTL_ANAR_10FD		0x0040	/* 1=10Base-T full duplex supported */
									/* default = 1 */

#define	RTL_ANAR_10			0x0020	/* 1=10Base-T supported */
									/* default = 1 */

#define	RTL_ANAR_SELECTOR	0x0001	/* Binary Encoded Selector */
									/* Currently only CSMA/CD <00001> */
									/* Supported */
									/* default = 00001 */

/*  EEPROM_Ctrl bits. */

/* eeprom contents */
    
#define RTL_EE_OEM_ADR0		0x0E
#define	RTL_EE_OEM_ADR1		0x11
#define RTL_EE_OEM_ADR2		0x13

#define	RTL_VENDOR_ID		0x10ec
#define	RTL_VENDOR_ID_MIS	0x1113
#define	RTL_8129_DEV_ID		0x8129
#define	RTL_8139_DEV_ID 	0x8139
#define	RTL_MIS_DEV_ID 		0x1211

#define	RTL_DEV_MASK		0xffff
#define	RTL_IO_SIZE			0x80

#define RTL_TIMEOUT			1000

#define RTL_WIN_0    		0

#define RTL_MIN_FBUF     100    /* Minimum size of the first buffer in a */
                               /* chain. */

typedef struct rtl_mii_frame {
	UINT8			mii_stdelim;
	UINT8			mii_opcode;
	UINT8			mii_phyaddr;
	UINT8			mii_regaddr;
	UINT8			mii_turnaround;
	USHORT			mii_data;
} RTL_MII_FRAME ;

/*
 * MII constants
 */

#define RTL_MII_STARTDELIM	0x01
#define RTL_MII_READOP		0x02
#define RTL_MII_WRITEOP		0x01
#define RTL_MII_TURNAROUND	0x02

/*
 * Texas Instruments PHY identifiers
 */
#define TI_PHY_VENDORID		0x4000
#define TI_PHY_10BT			0x501F
#define TI_PHY_100VGPMI		0x502F

/*
 * These ID values are for the NS DP83840A 10/100 PHY
 */
#define NS_PHY_VENDORID		0x2000
#define NS_PHY_83840A		0x5C0F

/*
 * Level 1 10/100 PHY
 */
#define LEVEL1_PHY_VENDORID	0x7810
#define LEVEL1_PHY_LXT970	0x000F

/*
 * Intel 82555 10/100 PHY
 */
#define INTEL_PHY_VENDORID	0x0A28
#define INTEL_PHY_82555		0x015F

/*
 * SEEQ 80220 10/100 PHY
 */
#define SEEQ_PHY_VENDORID	0x0016
#define SEEQ_PHY_80220		0xF83F


#define RTL_PHY_UNKNOWN			6

#define RTL_PHYADDR_MIN			0x00
#define RTL_PHYADDR_MAX			0x1F

#define RTL_PHY_BMCR			0x00
#define RTL_PHY_BMSR			0x01
#define RTL_PHY_VENID			0x02
#define RTL_PHY_DEVID			0x03
#define RTL_PHY_ANAR			0x04
#define RTL_PHY_LPAR			0x05
#define RTL_PHY_ANEXP			0x06

#define RTL_PHY_ANAR_NEXTPAGE	0x8000
#define RTL_PHY_ANAR_RSVD0		0x4000
#define RTL_PHY_ANAR_TLRFLT		0x2000
#define RTL_PHY_ANAR_RSVD1		0x1000
#define RTL_PHY_ANAR_RSVD2		0x0800
#define RTL_PHY_ANAR_RSVD3		0x0400
#define RTL_PHY_ANAR_100BT4		0x0200
#define RTL_PHY_ANAR_100BTXFULL	0x0100
#define RTL_PHY_ANAR_100BTXHALF	0x0080
#define RTL_PHY_ANAR_10BTFULL	0x0040
#define RTL_PHY_ANAR_10BTHALF	0x0020
#define RTL_PHY_ANAR_PROTO4		0x0010
#define RTL_PHY_ANAR_PROTO3		0x0008
#define RTL_PHY_ANAR_PROTO2		0x0004
#define RTL_PHY_ANAR_PROTO1		0x0002
#define RTL_PHY_ANAR_PROTO0		0x0001

/*
 * These are the register definitions for the PHY (physical layer
 * interface chip).
 */
/*
 * PHY BMCR Basic Mode Control Register
 */

#define RTL_PHY_BMCR_RESET			0x8000
#define RTL_PHY_BMCR_LOOPBK			0x4000
#define RTL_PHY_BMCR_SPEEDSEL		0x2000
#define RTL_PHY_BMCR_AUTONEGENBL		0x1000
#define RTL_PHY_BMCR_RSVD0			0x0800	/* write as zero */
#define RTL_PHY_BMCR_ISOLATE		0x0400
#define RTL_PHY_BMCR_AUTONEGRSTR		0x0200
#define RTL_PHY_BMCR_DUPLEX			0x0100
#define RTL_PHY_BMCR_COLLTEST		0x0080
#define RTL_PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
#define RTL_PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */

/*
 * RESET: 1 == software reset, 0 == normal operation
 * Resets status and control registers to default values.
 * Relatches all hardware config values.
 *
 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
 *
 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
 * Link speed is selected byt his bit or if auto-negotiation if bit
 * 12 (AUTONEGENBL) is set (in which case the value of this register
 * is ignored).
 *
 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
 * determine speed and mode. Should be cleared and then set if PHY configured
 * for no autoneg on startup.
 *
 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
 *
 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
 *
 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
 *
 * COLLTEST: 1 == collision test enabled, 0 == normal operation
 */

/* 
 * PHY, BMSR Basic Mode Status Register 
 */   
#define RTL_PHY_BMSR_100BT4			0x8000
#define RTL_PHY_BMSR_100BTXFULL		0x4000
#define RTL_PHY_BMSR_100BTXHALF		0x2000
#define RTL_PHY_BMSR_10BTFULL		0x1000
#define RTL_PHY_BMSR_10BTHALF		0x0800
#define RTL_PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
#define RTL_PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
#define RTL_PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
#define RTL_PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
#define RTL_PHY_BMSR_MFPRESUP		0x0040
#define RTL_PHY_BMSR_AUTONEGCOMP	0x0020
#define RTL_PHY_BMSR_REMFAULT		0x0010
#define RTL_PHY_BMSR_CANAUTONEG		0x0008
#define RTL_PHY_BMSR_LINKSTAT		0x0004
#define RTL_PHY_BMSR_JABBER			0x0002
#define RTL_PHY_BMSR_EXTENDED		0x0001

/* ethernet media */

#define IFM_ETHER		0x00000020
#define	IFM_10_T		3		/* 10BaseT - RJ45 */
#define	IFM_10_2		4		/* 10Base2 - Thinnet */
#define	IFM_10_5		5		/* 10Base5 - AUI */
#define	IFM_100_TX		6		/* 100BaseTX - RJ45 */
#define	IFM_100_FX		7		/* 100BaseFX - Fiber */
#define	IFM_100_T4		8		/* 100BaseT4 - 4 pair cat 3 */
#define	IFM_100_VG		9		/* 100VG-AnyLAN */
#define	IFM_100_T2		10		/* 100BaseT2 */

/* Shared media sub-types */

#define	IFM_AUTO		0	/* Autoselect best media */
#define	IFM_MANUAL		1	/* Jumper/dipswitch selects media */
#define	IFM_NONE		2	/* Deselect all media */

/* Shared options */

#define IFM_FDX			0x00100000	/* Force full duplex */
#define	IFM_HDX			0x00200000	/* Force half duplex */
#define IFM_FLAG0		0x01000000	/* Driver defined flag */
#define IFM_FLAG1		0x02000000	/* Driver defined flag */
#define IFM_FLAG2		0x04000000	/* Driver defined flag */
#define	IFM_LOOP		0x08000000	/* Put hardware in loopback */

/* Masks */

#define	IFM_NMASK		0x000000e0	/* Network type */
#define	IFM_TMASK		0x0000000f	/* Media sub-type */
#define	IFM_IMASK		0xf0000000	/* Instance */
#define	IFM_ISHIFT		28		/* Instance shift */
#define	IFM_OMASK		0x0000ff00	/* Type specific options */
#define	IFM_GMASK		0x0ff00000	/* Global options */

/* Status bits */

#define	IFM_AVALID		0x00000001	/* Active bit valid */
#define	IFM_ACTIVE		0x00000002	/* Iface bound to working net */

/*
 * Macros to extract various bits of information from the media word.
 */
#define	IFM_TYPE(x)	((x) & IFM_NMASK)
#define	IFM_SUBTYPE(x)	((x) & IFM_TMASK)
#define	IFM_INST(x)	(((x) & IFM_IMASK) >> IFM_ISHIFT)

#define RTL_FLAG_FORCEDELAY	1
#define RTL_FLAG_SCHEDDELAY	2
#define RTL_FLAG_DELAYTIMEO	3	


/* The definition of the driver control structure */

typedef struct rtl_device
    {	
    END_OBJ     end;			/* The class we inherit from. */
    rtl_ib       *ib;			/* ptr to Initialization Block */
    UINT8		devType;	    /* 8129, 8139A or 8139B */
    int			unit;			/* unit number */
	UINT8		phy_addr;		/* PHY address */
    int			nextDesc;		/* Next Tx Descriptor */
    int			freeDesc;		/* Free Tx Descriptors */
    char		*pDescMem[RTL_NUM_TX_DESC]; /* Pointer to buffer */
	char 		txmemspace[RTL_NUM_TX_DESC * RTL81x9_BUFSIZE];
    ULONG		rmdNext;		/* index into the next Rx Pkt */
    char		*ptrRxBufSpace;	/* Ptr to the Rx Buffer Pool */
    int			rringSize;		/* RMD ring size */
    int 		rringLen; 		/* RMD ring length (bytes) */
    RTL_RMD		*pRring;		/* RMD ring start */
    int         ivec;           /* interrupt vector */
    int         ilevel;         /* interrupt level */
    UINT32		devAdrs;		/* device register RAP */
    UINT16		csr3B;			/* csr3 value board specific */
    char*       pShMem;         /* real ptr to shared memory */
    char*       memBase;        /* RTL memory pool base */
    char*       memAdrs;        /* RTL memory pool base */
    int         memSize;        /* RTL memory pool size */
    int         memWidth;       /* width of data port */
    int         offset;
    int         csr0Errs;       /* count of csr0 errors */
    UINT32      flags;			/* Our local flags */
    UINT32		pciMemBase;		/* memory base as seen from PCI*/
    UCHAR		enetAddr[6];	/* ethernet address */
    CACHE_FUNCS cacheFuncs;     /* cache function pointers */
    BOOL		txBlocked; 		/* transmit flow control */
    CL_POOL_ID  pClPoolId;
    END_ERR     lastError;      /* Last error passed to muxError */
    BOOL        errorHandling;  /* task level error handling */
    u_short     errorStat;      /* error status */
    } RTL81X9END_DEVICE;



/* Configuration items */

#define RMD_SIZ	sizeof(RTL_RMD)
#define IB_SIZ	sizeof(rtl_ib)

#ifdef __cplusplus
}
#endif

#endif /* __INCrtl81x9Endh */