module lcd_test(clkin,DE,CLKOUT,HSYNC,YSYNC,PON,HL,JGND,DATA);
input clkin;
output DE,CLKOUT,HSYNC,YSYNC,PON,HL;
output [15:0]DATA;
output [7:0]JGND;
reg DE,CLKOUT,HSYNC,YSYNC,DEX,PON,TONG,HL;
reg [15:0] DATA;
reg [9:0] temp;
reg [9:0] tmp;
reg [9:0] temp1;
reg [10:0] temp3;
reg [10:0] temp4;
reg [9:0] temp2;
reg [7:0] JGND;

initial
begin

	DE=1'b0;
	CLKOUT=1'b0;
	HSYNC=1'b0;
	YSYNC=1'b0;
	temp=0;
	tmp=0;
	JGND=8'h00;
	HL=1'b1;
	temp1=0;
	temp2=0;
	temp3=0;
	temp4=0;
	PON=1'b0;
	TONG=1'b0;
	DATA=16'h0000;
end

always@(posedge clkin)
begin
	if(temp==10'd84)
	begin	
		CLKOUT=~CLKOUT;
		temp=0;
	end
	else
	
		temp=temp+1'b1;

end




always@(posedge CLKOUT)
begin
	temp1=temp1+1'b1;
	if(temp1==6'd41)
	begin
		HSYNC=1'b1;
	end
		
	else if(DEX&temp1==6'd45)
	begin
		DE=1'b1;
		TONG=1'b1;
		PON=1'b1;

	end


		
	else if(temp1==10'd533)
	begin	
		HSYNC=1'b0;
		DE=1'b0;
		TONG=1'b0;
		temp1=0;
		JGND=8'h00;
		end
end

always@(posedge HSYNC)
begin
	temp2=temp2+1'b1;
	temp3=temp2+temp4;
	if(temp2==4'd11)
		begin
		YSYNC=1'b1;
		end
	else if(temp2==4'd13)
		DEX=1'b1;
	
	else if(temp2==9'd286)
		DEX=1'b0;
		
			
	 if(temp3==4'd14)
		DATA=16'b0000_0000_0001_1111;	
			
		if(temp3==9'd60)
		DATA=16'b0000_0111_1110_0000;
		
		if(temp3==9'd105)
		//DATA=24'hff0000;
		DATA=16'b1111_1000_0000_0000;
				
		if(temp3==9'd150)
		//DATA=24'h00ffff;
		DATA=16'b0000_0111_1111_1111;
		
		if(temp3==9'd195)
		//DATA=24'hffff00;
		DATA=16'b1111_1111_1110_0000;
		
		if(temp3==9'd239)
		//DATA=24'hff00ff;
		DATA=16'b1111_1000_0001_1111;
		
		if(temp3==9'd284)
		DATA=16'hffff;
		//DATA=16'b0000_0000_0000_0000;
		
		if(temp3==9'd329)
		//DATA=24'h0000ff;
		DATA=16'b0000_0000_0000_0000;
		
		if(temp3==9'd374)
		//DATA=24'h00ff00;
		DATA=16'b0000_0111_1110_0000;
		
		if(temp3==9'd419)
		//DATA=24'hff0000;
		DATA=16'b1111_1000_0000_0000;
				
		if(temp3==9'd464)
		//DATA=24'h00ffff;
		DATA=16'b0000_0111_1111_1111;
		
		if(temp3==10'd509)
		//DATA=24'hffff00;
		DATA=16'b1111_1111_1110_0000;
		
		if(temp3==10'd554)
		//DATA=24'hff00ff;
		DATA=16'b1111_1000_0001_1111;
		
		if(temp3==10'd599)
		//DATA=24'h0000ff;
		DATA=16'b0000_0000_0001_1111;
	
	if(temp2==9'd289)
	begin
		YSYNC=1'b0;
		temp2=0;
		temp4=temp4+4'd1;
		if(temp4==9'd320)
			begin			
			temp4=0;
			end
	end
end
endmodule