Fitter report for TFT
Wed Jan 12 20:45:45 2011
Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Parallel Compilation
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. Bidir Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB-wide Signals
 21. LAB Signals Sourced
 22. LAB Signals Sourced Out
 23. LAB Distinct Inputs
 24. Fitter Device Options
 25. Estimated Delay Added for Hold Timing
 26. Fitter Messages
 27. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Wed Jan 12 20:45:45 2011         ;
; Quartus II Version    ; 9.1 Build 304 01/25/2010 SP 1 SJ Full Version ;
; Revision Name         ; TFT                                           ;
; Top-level Entity Name ; TFT                                           ;
; Family                ; MAX II                                        ;
; Device                ; EPM570T144C5                                  ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 357 / 570 ( 63 % )                            ;
; Total pins            ; 72 / 116 ( 62 % )                             ;
; Total virtual pins    ; 0                                             ;
; UFM blocks            ; 0 / 1 ( 0 % )                                 ;
+-----------------------+-----------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                              ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                     ; Setting                        ; Default Value                  ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                     ; EPM570T144C5                   ;                                ;
; Minimum Core Junction Temperature                                          ; 0                              ;                                ;
; Maximum Core Junction Temperature                                          ; 85                             ;                                ;
; Fit Attempts to Skip                                                       ; 0                              ; 0.0                            ;
; Device I/O Standard                                                        ; 3.3-V LVTTL                    ;                                ;
; Use smart compilation                                                      ; Off                            ; Off                            ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                             ; On                             ;
; Enable compact report table                                                ; Off                            ; Off                            ;
; Use TimeQuest Timing Analyzer                                              ; Off                            ; Off                            ;
; Router Timing Optimization Level                                           ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                                ; 1.0                            ; 1.0                            ;