Release 8.2.03i Map I.34Xilinx Mapping Report File for Design 'LCD1602'Design Information------------------Command Line   : C:\Xilinx\bin\nt\map.exe -ise C:/Xilinx/spartan
3E/jupiter/LCD/LCD.ise -intstyle ise -p xc3s500e-fg320-4 -cm area -pr b -k 4 -c
100 -o LCD1602_map.ncd LCD1602.ngd LCD1602.pcf Target Device  : xc3s500eTarget Package : fg320Target Speed   : -4Mapper Version : spartan3e -- $Revision: 1.34.32.1 $Mapped Date    : Fri Sep 21 09:15:25 2007Design Summary--------------Number of errors:      0Number of warnings:    2Logic Utilization:  Number of Slice Flip Flops:          62 out of   9,312    1%  Number of 4 input LUTs:             114 out of   9,312    1%Logic Distribution:  Number of occupied Slices:                          104 out of   4,656    2%    Number of Slices containing only related logic:     104 out of     104  100%    Number of Slices containing unrelated logic:          0 out of     104    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:            140 out of   9,312    1%  Number used as logic:                114  Number used as a route-thru:          26  Number of bonded IOBs:                9 out of     232    3%    IOB Flip Flops:                     4  Number of GCLKs:                     2 out of      24    8%Total equivalent gate count for design:  1,464Additional JTAG gate count for IOBs:  432Peak Memory Usage:  160 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_LCD_Clk/LCD_Clk_BUFG" (output signal=LCD_Clk) has a
   mix of clock and non-clock loads. The non-clock loads are:   Pin D of LCD_ClkWARNING:Pack:266 - The function generator _mux0023<2>31 failed to merge with F5
   multiplexer _mux0023<5>_f5.  There is a conflict for the FXMUX.  The design
   will exhibit suboptimal timing.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "CLK_BUFGP" (output signal=CLK_BUFGP),   BUFG symbol "LCD_Clk_BUFG" (output signal=LCD_Clk)INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | IOB Type         | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IBUF/IFD  ||                                    |                  |           |             | Strength | Rate |              |          | Delay     |+-----------------------------------------------------------------------------------------------------------------------------------------+| CLK                                | IBUF             | INPUT     | LVTTL       |          |      |              |          | 0 / 0     || LCD_EN                             | IOB              | OUTPUT    | LVTTL       | 2        | SLOW |              |          | 0 / 0     || LCD_RS                             | IOB              | OUTPUT    | LVTTL       | 2        | SLOW |              |          | 0 / 0     || LCD_RW                             | IOB              | OUTPUT    | LVTTL       | 2        | SLOW |              |          | 0 / 0     || Reset                              | IBUF             | INPUT     | LVTTL       |          |      |              | PULLUP   | 0 / 0     || data<0>                            | IOB              | OUTPUT    | LVTTL       | 2        | SLOW | OFF1         |          | 0 / 0     || data<1>                            | IOB              | OUTPUT    | LVTTL       | 2        | SLOW | OFF1         |          | 0 / 0     || data<2>                            | IOB              | OUTPUT    | LVTTL       | 2        | SLOW | OFF1         |          | 0 / 0     || data<3>                            | IOB              | OUTPUT    | LVTTL       | 2        | SLOW | OFF1         |          | 0 / 0     |+-----------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Area Group Information----------------------  No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration Strings