Release 8.2.03i par I.34Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.JUPITER::  Fri Sep 21 09:16:08 2007par -w -intstyle ise -ol std -t 1 LCD1602_map.ncd LCD1602.ncd LCD1602.pcf Constraints file: LCD1602.pcf.Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx.   "LCD1602" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".Device speed data version:  "PRODUCTION 1.26 2006-08-18".Design Summary Report: Number of External IOBs                           9 out of 232     3%   Number of External Input IOBs                  2      Number of External Input IBUFs              2        Number of LOCed External Input IBUFs      2 out of 2     100%   Number of External Output IOBs                 7      Number of External Output IOBs              7        Number of LOCed External Output IOBs      7 out of 7     100%   Number of External Bidir IOBs                  0   Number of BUFGMUXs                  2 out of 24      8%   Number of Slices                  104 out of 4656    2%      Number of SLICEMs                0 out of 2328    0%Overall effort level (-ol):   Standard Placer effort level (-pl):    High Placer cost table entry (-t): 1Router effort level (-rl):    Standard Starting PlacerPhase 1.1Phase 1.1 (Checksum:989934) REAL time: 38 secs Phase 2.7Phase 2.7 (Checksum:1312cfe) REAL time: 40 secs Phase 3.31Phase 3.31 (Checksum:1c9c37d) REAL time: 40 secs Phase 4.2.......................Phase 4.2 (Checksum:989e5f) REAL time: 45 secs Phase 5.30Phase 5.30 (Checksum:2faf07b) REAL time: 45 secs Phase 6.8.....................................................................................................Phase 6.8 (Checksum:a3b2f7) REAL time: 46 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 46 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 46 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 46 secs Writing design to file LCD1602.ncdTotal REAL time to Placer completion: 46 secs Total CPU time to Placer completion: 10 secs Starting RouterPhase 1: 641 unrouted;       REAL time: 53 secs Phase 2: 586 unrouted;       REAL time: 53 secs Phase 3: 161 unrouted;       REAL time: 53 secs Phase 4: 161 unrouted; (9906)      REAL time: 53 secs Phase 5: 172 unrouted; (0)      REAL time: 53 secs Phase 6: 0 unrouted; (0)      REAL time: 54 secs Phase 7: 0 unrouted; (0)      REAL time: 54 secs Phase 8: 0 unrouted; (0)      REAL time: 54 secs Phase 9: 0 unrouted; (0)      REAL time: 54 secs WARNING:Route:447 - CLK Net:LCD_Clk may have excessive skew because    1 NON-CLK pins failed to route using a CLK template.Total REAL time to Router completion: 54 secs Total CPU time to Router completion: 14 secs Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|             LCD_Clk | BUFGMUX_X2Y10| No   |   42 |  0.062     |  0.196      |+---------------------+--------------+------+------+------------+-------------+|           CLK_BUFGP | BUFGMUX_X1Y11| No   |   13 |  0.008     |  0.176      |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays.   The Delay Summary ReportThe NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.869   The MAXIMUM PIN DELAY IS:                               3.065   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.424   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------         393         218          25           2           0           0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.   This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of                                            |            |            | Levels | Slack      |errors   ------------------------------------------------------------------------------------------------------  Autotimespec constraint for clock net LCD | N/A        | 8.705ns    | 3      | N/A        | N/A       _Clk                                      |            |            |        |            |         ------------------------------------------------------------------------------------------------------  Autotimespec constraint for clock net CLK | N/A        | 4.614ns    | 1      | N/A        | N/A       _BUFGP                                    |            |            |        |            |         ------------------------------------------------------------------------------------------------------All constraints were met.INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the    constraint does not cover any paths or that it has no requested value.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 58 secs Total CPU time to PAR completion: 14 secs Peak Memory Usage:  152 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 1Number of info messages: 1Writing design to file LCD1602.ncdPAR done!