/***************************************************************************    r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit*    Written 2003 by Timothy Legge <tlegge@rogers.com>**    This program is free software; you can redistribute it and/or modify*    it under the terms of the GNU General Public License as published by*    the Free Software Foundation; either version 2 of the License, or*    (at your option) any later version.**    This program is distributed in the hope that it will be useful,*    but WITHOUT ANY WARRANTY; without even the implied warranty of*    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the*    GNU General Public License for more details.**    You should have received a copy of the GNU General Public License*    along with this program; if not, write to the Free Software*    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.**    Portions of this code based on:*	r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver * 		for Linux kernel 2.4.x.**    Written 2002 ShuChen <shuchen@realtek.com.tw>*	  See Linux Driver for full information*	*    Linux Driver Version 1.27a, 10.02.2002* *    Thanks to:*    	Jean Chen of RealTek Semiconductor Corp. for*    	providing the evaluation NIC used to develop *    	this driver.  RealTek's support for Etherboot *    	is appreciated.*    	*    REVISION HISTORY:*    ================**    v1.0	11-26-2003	timlegge	Initial port of Linux driver*    v1.5	01-17-2004	timlegge	Initial driver output cleanup*    *    Indent Options: indent -kr -i8***************************************************************************//* to get some global routines like printf */#include "etherboot.h"/* to get the interface to the body of the program */#include "nic.h"/* to get the PCI support functions, if this is a PCI NIC */#include "pci.h"#include "timer.h"#define drv_version "v1.5"#define drv_date "01-17-2004"typedef unsigned char u8;typedef signed char s8;typedef unsigned short u16;typedef signed short s16;typedef unsigned int u32;typedef signed int s32;static u32 ioaddr;/* Condensed operations for readability. */#define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))#define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))/* media options */#define MAX_UNITS 8static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };/* Maximum events (Rx packets, etc.) to handle at each interrupt. */static int max_interrupt_work = 20;/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */static int multicast_filter_limit = 32;/* MAC address length*/#define MAC_ADDR_LEN	6/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/#define MAX_ETH_FRAME_SIZE	1536#define TX_FIFO_THRESH 256	/* In bytes */#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer.  */#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */#define EarlyTxThld 	0x3F	/* 0x3F means NO early transmit */#define RxPacketMaxSize	0x0800	/* Maximum size supported is 16K-1 */#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */#define NUM_TX_DESC	1	/* Number of Tx descriptor registers */#define NUM_RX_DESC	4	/* Number of Rx descriptor registers */#define RX_BUF_SIZE	1536	/* Rx Buffer size */#define RTL_MIN_IO_SIZE 0x80#define TX_TIMEOUT  (6*HZ)/* write/read MMIO register */#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))#define RTL_R8(reg)		readb (ioaddr + (reg))#define RTL_R16(reg)		readw (ioaddr + (reg))#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))enum RTL8169_registers {	MAC0 = 0,		/* Ethernet hardware address. */	MAR0 = 8,		/* Multicast filter. */	TxDescStartAddr = 0x20,	TxHDescStartAddr = 0x28,	FLASH = 0x30,	ERSR = 0x36,	ChipCmd = 0x37,	TxPoll = 0x38,	IntrMask = 0x3C,	IntrStatus = 0x3E,	TxConfig = 0x40,	RxConfig = 0x44,	RxMissed = 0x4C,	Cfg9346 = 0x50,	Config0 = 0x51,	Config1 = 0x52,	Config2 = 0x53,	Config3 = 0x54,	Config4 = 0x55,	Config5 = 0x56,	MultiIntr = 0x5C,	PHYAR = 0x60,	TBICSR = 0x64,	TBI_ANAR = 0x68,	TBI_LPAR = 0x6A,	PHYstatus = 0x6C,	RxMaxSize = 0xDA,	CPlusCmd = 0xE0,	RxDescStartAddr = 0xE4,	EarlyTxThres = 0xEC,	FuncEvent = 0xF0,	FuncEventMask = 0xF4,	FuncPresetState = 0xF8,	FuncForceEvent = 0xFC,};enum RTL8169_register_content {	/*InterruptStatusBits */	SYSErr = 0x8000,	PCSTimeout = 0x4000,	SWInt = 0x0100,	TxDescUnavail = 0x80,	RxFIFOOver = 0x40,	RxUnderrun = 0x20,	RxOverflow = 0x10,	TxErr = 0x08,	TxOK = 0x04,	RxErr = 0x02,	RxOK = 0x01,	/*RxStatusDesc */	RxRES = 0x00200000,	RxCRC = 0x00080000,	RxRUNT = 0x00100000,	RxRWT = 0x00400000,	/*ChipCmdBits */	CmdReset = 0x10,	CmdRxEnb = 0x08,	CmdTxEnb = 0x04,	RxBufEmpty = 0x01,	/*Cfg9346Bits */	Cfg9346_Lock = 0x00,	Cfg9346_Unlock = 0xC0,	/*rx_mode_bits */	AcceptErr = 0x20,	AcceptRunt = 0x10,	AcceptBroadcast = 0x08,	AcceptMulticast = 0x04,	AcceptMyPhys = 0x02,	AcceptAllPhys = 0x01,	/*RxConfigBits */	RxCfgFIFOShift = 13,	RxCfgDMAShift = 8,	/*TxConfigBits */	TxInterFrameGapShift = 24,	TxDMAShift = 8,		/* DMA burst value (0-7) is shift this many bits */	/*rtl8169_PHYstatus */	TBI_Enable = 0x80,	TxFlowCtrl = 0x40,	RxFlowCtrl = 0x20,	_1000bpsF = 0x10,	_100bps = 0x08,	_10bps = 0x04,	LinkStatus = 0x02,	FullDup = 0x01,	/*GIGABIT_PHY_registers */	PHY_CTRL_REG = 0,	PHY_STAT_REG = 1,	PHY_AUTO_NEGO_REG = 4,	PHY_1000_CTRL_REG = 9,	/*GIGABIT_PHY_REG_BIT */	PHY_Restart_Auto_Nego = 0x0200,	PHY_Enable_Auto_Nego = 0x1000,	//PHY_STAT_REG = 1;	PHY_Auto_Neco_Comp = 0x0020,	//PHY_AUTO_NEGO_REG = 4;	PHY_Cap_10_Half = 0x0020,	PHY_Cap_10_Full = 0x0040,	PHY_Cap_100_Half = 0x0080,	PHY_Cap_100_Full = 0x0100,	//PHY_1000_CTRL_REG = 9;	PHY_Cap_1000_Full = 0x0200,	PHY_Cap_Null = 0x0,	/*_MediaType*/	_10_Half = 0x01,	_10_Full = 0x02,	_100_Half = 0x04,	_100_Full = 0x08,	_1000_Full = 0x10,	/*_TBICSRBit*/	TBILinkOK = 0x02000000,};static struct {	const char *name;	u8 version;		/* depend on RTL8169 docs */	u32 RxConfigMask;	/* should clear the bits supported by this chip */} rtl_chip_info[] = {	{"RTL-8169", 0x00, 0xff7e1880,},};enum _DescStatusBit {	OWNbit = 0x80000000,	EORbit = 0x40000000,	FSbit = 0x20000000,	LSbit = 0x10000000,};struct TxDesc {	u32 status;	u32 vlan_tag;	u32 buf_addr;	u32 buf_Haddr;};struct RxDesc {	u32 status;	u32 vlan_tag;	u32 buf_addr;	u32 buf_Haddr;};/* Define the TX Descriptor */static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];//	__attribute__ ((aligned(256)));/* Create a static buffer of size RX_BUF_SZ for eachTX Descriptor.  All descriptors point to apart of this buffer */static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];/* Define the RX Descriptor */static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];  //  __attribute__ ((aligned(256)));/* Create a static buffer of size RX_BUF_SZ for eachRX Descriptor   All descriptors point to apart of this buffer */static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];struct rtl8169_private {	void *mmio_addr;	/* memory map physical address */	int chipset;	unsigned long cur_rx;	/* Index into the Rx descriptor buffer of next Rx pkt. */	unsigned long cur_tx;	/* Index into the Tx descriptor buffer of next Rx pkt. */	unsigned long dirty_tx;	unsigned char *TxDescArrays;	/* Index of Tx Descriptor buffer */	unsigned char *RxDescArrays;	/* Index of Rx Descriptor buffer */	struct TxDesc *TxDescArray;	/* Index of 256-alignment Tx Descriptor buffer */	struct RxDesc *RxDescArray;	/* Index of 256-alignment Rx Descriptor buffer */	unsigned char *RxBufferRings;	/* Index of Rx Buffer  */	unsigned char *RxBufferRing[NUM_RX_DESC];	/* Index of Rx Buffer array */	unsigned char *Tx_skbuff[NUM_TX_DESC];} tpx;static struct rtl8169_private *tpc;static const u16 rtl8169_intr_mask =    SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |    TxOK | RxErr | RxOK;static const unsigned int rtl8169_rx_config =    (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);void mdio_write(int RegAddr, int value){	int i;	RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);	udelay(1000);	for (i = 2000; i > 0; i--) {		// Check if the RTL8169 has completed writing to the specified MII register		if (!(RTL_R32(PHYAR) & 0x80000000)) {			break;		} else {			udelay(100);		}	}}int mdio_read(int RegAddr){	int i, value = -1;	RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);	udelay(1000);	for (i = 2000; i > 0; i--) {		// Check if the RTL8169 has completed retrieving data from the specified MII register		if (RTL_R32(PHYAR) & 0x80000000) {			value = (int) (RTL_R32(PHYAR) & 0xFFFF);			break;		} else {			udelay(100);		}	}	return value;}#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))static int rtl8169_init_board(struct pci_device *pdev){	int i, pm_cap;	unsigned long rtreg_base, rtreg_len;	u32 tmp;	rtreg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);	rtreg_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);	// check for weird/broken PCI region reporting	if (rtreg_len < RTL_MIN_IO_SIZE) {		printf("Invalid PCI region size(s), aborting\n");	}	adjust_pci_device(pdev);	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);	// ioremap MMIO region 	ioaddr = (unsigned long) ioremap(rtreg_base, rtreg_len);	if (ioaddr == 0)		printf("Error cannot remap MMIO, aborting\n");	tpc->mmio_addr = &ioaddr;	// Soft reset the chip. 	RTL_W8(ChipCmd, CmdReset);	// Check that the chip has finished the reset.	for (i = 1000; i > 0; i--)		if ((RTL_R8(ChipCmd) & CmdReset) == 0)			break;		else			udelay(10);	// identify chip attached to board	tmp = RTL_R32(TxConfig);	tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;	for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)		if (tmp == rtl_chip_info[i].version) {			tpc->chipset = i;			goto match;		}	//if unknown chip, assume array element #0, original RTL-8169 in this case	printf("PCI device %s: unknown chip version, assuming RTL-8169\n");	printf("PCI device: TxConfig = 0x%hX\n",	       (unsigned long) RTL_R32(TxConfig));	tpc->chipset = 0;      match:	return 0;}/**************************************************************************POLL - Wait for a frame***************************************************************************/