head	1.4;access;symbols;locks	root:1.4; strict;comment	@ * @;1.4date	99.12.01.04.12.01;	author root;	state Exp;branches;next	1.3;1.3date	99.08.24.00.50.26;	author root;	state Exp;branches;next	1.2;1.2date	99.08.22.03.38.04;	author root;	state Exp;branches;next	1.1;1.1date	99.08.18.00.22.29;	author root;	state Exp;branches;next	;desc
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1.4log@Updated for 0.9.2 catchup build.@text@/*
 * Port IO routines + emulation of low level layers from ltmodem.sys.
 *
 *  Copyright (c) 1999 Richard J.M. Close
 *  Copyright (c) 1999 Pavel Machek <pavel@@ucw.cz>
 *  Copyright (c) 1999 Jamie Lokier
 *
 *  Can be freely distributed and used under the terms of the GNU GPL.
 */

#include "portIO.h"

// IO port subroutines etc.
// The first section has routines based on the NT HAL library calls.
// The implementation in this file is not a copy of the real code but
// has the same interface and is designed to be used by user space processes.
// A version for a device driver will be implemented at a later date, this
// will be much simpler as more system resources are available to drivers.

// Also note that the pausing versions of inb, inw etc. (inb_p inw_p etc.)
// have been used.

// Low level interface
//==========================================================================================
//
// The following section contains routines that have been "reverse engineered" from those in
// in the NT driver code. The functions are named according to thier names in original
// lucent .sys driver.


// Port variables - these are initialised by port_io_init. The values below are purely
// for illustration purposes.
// PCIOutAddr holds a (?) base port address and PCIInAddr has this base + 4.
unsigned int PCIOutAddr = 0x6200;
unsigned int PCIInAddr = 0x6204;

// I think this initial value is wrong. I need to find out how this is being set.
// In read_Blacktip_Resource it is set to 118h, 110h, 108h, or 100h. This may be a clue!
// dp_run_rom sets it to 260h.
unsigned int BaseAddress =0x6300;
 
unsigned int BaseAddress2 = 0x6300; 
unsigned int ComAddress = 0;
unsigned int word_59ED7 = 0;

// Set up in dp_board_enable with values derived from BaseAddress, ComAddress and word_59ED7.
unsigned int BaseAddressIndex = 0;
unsigned int BaseAddressData = 0;

unsigned char BaseValue = 0;

// DSP RAM read fail count. What happens if this is >255 ?
unsigned char dp_readram_failcnt = 0;


void Init_Mars(void)
{
  Write_mdm_byte(0x37, 0x22);
  Write_mdm_byte(0x30,    1);
  Write_mdm_byte(0x3c, 0xff);
  Write_mdm_byte(0x3e,	  1);
}

// Main initialisation routine called from ltmodem.c code.
void port_io_init(unsigned int Portbase1, unsigned int Portbase2)
{
  // Which portbase do we use? Pavel used the second so ...
  BaseAddress = Portbase2;

  printf( "Initialising with ports at %x and %x, ",
          Portbase1, Portbase2 );
  printf( "assuming portbase at %x.\n", BaseAddress );

  // Set up other portbases.
  PCIOutAddr = Portbase1;
  PCIInAddr = Portbase1 + 4;

  // Grab access to all the IO ports.
  if (iopl(3) < 0) {
    perror("portIO: iopl(3) failed");
    fprintf(stderr, "This program must be run as root.\n");
  }
}

// Places args in a long word to go to port, then reads back.
unsigned int PciRead_dword (unsigned char arg1, unsigned char arg2, unsigned char arg3)
{
  unsigned int ecx;
  unsigned char al;

  // shl al, 03h  (al = arg1). shift 3 left, ie. mult by 8.
  // and cl, 07h (cl = arg3).  mask off all but last 3 bits.
  // or al, cl                 OR the results.
  al = (arg1 * 8) | (arg3 & 7);

  //xor ecx, ecx -> ecx = 0 !
  //mov ch, al                 set byte 1 to above result.
  //mov  cl , byte ptr [ esp + 8 ]
  ecx = (256 * al) + arg2;         // put second arg in byte0. 
  
  // or ecx , 080000000h    Set most sig bit.
  ecx = ecx | 0x80000000; 

  outw_p (ecx, PCIOutAddr);
  //WRITE_PORT_ULONG (PCIOutAddr, ecx);
 
  return (inw_p (PCIInAddr));
  //	ret 0Ch			;0x00025425 :	c20c00 wind esp back 12 bytes.
}

unsigned int PciRead_word (unsigned char arg1, unsigned char arg2, unsigned char arg3)
{
  unsigned int dataOut;
  unsigned short readPort;

  dataOut = (256 * (arg1 * 8) | (arg3 & 7)) + arg3;
  dataOut = dataOut | 0x80000000; 
  
  outw_p (dataOut, PCIOutAddr);

  readPort = PCIInAddr | (arg2 & 2);
  return (inb_p (readPort));
}

void PciWrite_dword (unsigned int arg1, unsigned int arg2, unsigned int* ptrValue)
{
  unsigned int eax, ecx, Value;

  ecx = arg1 * 2084; // shl ecx, 0xBh
  ecx = ecx & 0x0000ffff;  //movzx ecx, cx

  eax = arg2 & 0xFF;
  eax = eax | ecx;
  eax = eax | 0x80000000;
   
  outw_p (eax, PCIOutAddr);
   
  Value = *ptrValue;
  outw_p (Value, PCIInAddr);
}

unsigned char Read_mdm_byte (unsigned int offset)
{
  return inb_p (BaseAddress + offset);
}

// Place value in port (base address in BaseAddress) plus offset.
void Write_mdm_byte (unsigned int portOffset, unsigned char value)
{
  outb_p (value, (BaseAddress + portOffset));
}

// Place value in port (base address in BaseAddress) plus offset.
void Write_mdm_word (unsigned int portOffset, unsigned short value)
{
  outw_p (value, (BaseAddress + portOffset));
}

void dp_out_port (int arg)
{
  outb_p (BaseValue, BaseAddressIndex);

  // arg is at [esp + 8], (4 for arg + 4 for push esi).
  outb_p (arg, BaseAddressData);
}

int dp_in_port(void)
{
  outb_p (BaseValue, BaseAddressIndex);
  return inb_p (BaseAddressData);
}

void dp_regwrite (unsigned int port, unsigned char val)
{
  BaseValue = port;
  BaseAddressIndex = BaseAddress;
  dp_out_port(val);
}

unsigned int dp_regread (unsigned int port)
{
  BaseValue = port;
  if (port <= 0x7f) {
    BaseAddressIndex = BaseAddress;
    return dp_in_port();
  }
  if (port < 0xa0) {
    BaseAddressIndex = BaseAddress2;
    return dp_in_port();
  }
  if (port <= 0xcf) {
    BaseAddressIndex = BaseAddress;
    return dp_in_port();
  }
  BaseAddressIndex = BaseAddress2;
  return dp_in_port();
}

void dp_int_regwrite(unsigned int port, unsigned int val)
{
  outb_p(port, BaseAddress);
  outb_p(val, BaseAddressData);
}

int dp_int_regread(unsigned int port)
{
  if (port <= 0x7f) {
    outb_p(port, BaseAddress);
    return inb_p(BaseAddressData);
  }
  if (port < 0xa0) {
    outb_p(port, BaseAddress + 2);
    return inb_p(BaseAddressData);
  }
  if (port <= 0xcf) {
    outb_p(port, BaseAddress);
    return inb_p(BaseAddressData);
  }
  outb_p(port, BaseAddress + 2);
  return inb_p(BaseAddressData);
}

int dp_dsp_regread (unsigned int arg)
{
  dp_byte_f = 0;
  dp_regwrite(0xD8, 0x18);
  dp_regwrite(0x36, arg);
  dp_regwrite(0x37, 0x06);
  dp_cmd_timer = x_current_time();
  while(1) {
    if (!dp_byte_f) {
      if (x_elapsed_time(dp_cmd_timer) < 0xc8)
	     continue;
    }
    if (dp_byte_f != 2) {
      dp_regwrite(0xD8, 0xFF);
      dp_byte_e = 0;
    }
    //printf("dp_dsp_regread: exiting with dp_byte_f = %d.\n", dp_byte_f);
    return dp_byte_e;
  }
}

int dp_read_dsp_ram(int where)
{
  dp_byte_f = 0;
  dp_regwrite(0xd8, 0x18);
  dp_regwrite(0x34, where);
  dp_regwrite(0x35, (where & 0xff00) / 256);
  dp_regwrite(0x37, 4);
  dp_cmd_timer = x_current_time();

  do {
    if (dp_byte_f != 0)
      break;
  } while (x_elapsed_time(dp_cmd_timer) < 0xc8);

  if (dp_byte_f != 1) {
    dp_regwrite(0xd8, 0xff);
    dp_byte_e = 0;
    dp_byte_d = 0;
    if (x_dsp_mars)
      Write_mdm_word(0x3c, 0x1ff);

	// Increment fail count.
    dp_readram_failcnt++;
  }
  else
    // Clear fail count.
    dp_readram_failcnt = 0;

  //printf("dp_read_dsp_ram: exiting with dp_byte_f = %d.\n", dp_byte_f);
  return ((dp_byte_e * 256) + dp_byte_d);
}

void
dp_write_dsp_ram(int addr, int val)
{
  dp_regwrite(0xd8, 0x18);
  dp_regwrite(0x32, val & 0xff);
  dp_regwrite(0x33, (val>>8) & 0xff);
  dp_regwrite(0x34, addr & 0xff);
  dp_regwrite(0x35, (addr>>8) & 0xff);
  dp_regwrite(0x37, 1);
  wait_for_core_read();
}

// This should be correct now.
void dp_modem_command (unsigned int command, unsigned int a4, unsigned int a8)
{

  if ((command == 0x0E) || (command == 0x0C)) 
	{
	  if ((dp_dsp_regread(0xB5) & 1) == 0)
		dp_regread(0xB0);
	  
	  if ((dp_dsp_regread(0xB5) & 0x10) == 0)
		{
		  printf("modem command: something active at 0xb5?\n");
		  dp_regwrite(0xB6, 0xEF);
		  dp_dsp_regread(0xB0);
		  dp_regwrite(0xB0, 0);
		}
 
	  dp_regwrite(0xB7, 0xFF);
	  dp_regwrite(0xB6, 0xEE);
	  dp_bamil_rd7 = 0xF3;
	  dp_regwrite(0xD7, 0xF3);
	  dp_dsp_data_in_progress = 0;
	}

  dp_regwrite(0xD8, 0x18);
  dp_regwrite(0x35, a8);
  dp_regwrite(0x36, a4);
  dp_regwrite(0x37, command);
  return wait_for_core_read();
}

void dp_modem_command_long(int a0, int a4, int a8, int aC, int a10)
{
  dp_regwrite(0xD8, 0x18);
  dp_regwrite(0x33, a10);
  dp_regwrite(0x34, aC);
  dp_regwrite(0x35, a8);
  dp_regwrite(0x36, a4);
  dp_regwrite(0x37, a0);
  return wait_for_core_read();
}

void x_output_init(void)
{
  if (x_dsp_mars) {
    dp_regwrite(0xb8, 1);
    dp_regwrite(0xb9, 1);
    dp_regwrite(0xba, 0x40);
    dp_regwrite(0xbb, 0x40);
    dp_regwrite(0xdb, 0x41);
    dp_regwrite(0xdc, 0);
  } else {
    dp_regwrite(0xb8, 0xe0);
    dp_regwrite(0xb9, 0xc0);
    dp_regwrite(0xba, 0x80);
    dp_regwrite(0xbb, 0x80);
    dp_regwrite(0xdb, 0);
    dp_regwrite(0xdc, 0);
  }
}


void x_output(int arg)
{
  //  unsigned int edi = 0;
  //  unsigned int ebx = 1;
  unsigned int state = arg;

  if (arg>0x2c)
    return;

// Start of main switch.
loc_2e6f1:
  switch(state) {
  // loc_2e71c
  case 0:
    x_output_init();
    set_boardid();
    x_set_hardware_options();
    return;

  // loc_2e730
  case 1:
    x_output_deinit();
    return;

  // loc_2e73a
  case 2:
    dp_modem_command(0x11, 0, 0);
    return;

  // loc_2e740
  case 3:
    dp_modem_command(0x12, 0, 0);
    return;

  case 4: case 5: case 6:
    return;

  // loc_2e706
  case 7:
    dp_modem_command(0x27, 1, 0);
    state = 0x18;
    goto loc_2e6f1;

  // loc_2e6f8
  case 8:
    dp_modem_command(0x27, 2, 0);
    state = 0x17;
    goto loc_2e6f1;

  // loc_2e7dc
  case 9:
    if (!x_dsp_mars) {
       dp_write_dsp_ram(0x0d, 0x40);
       return;
	}
    if (((byte_59EDE & 7) == 1) || ((byte_59EDE & 7) == 2)) {
       dp_write_dsp_ram(0x0d, 0x60);
       return;
	}
    dp_write_dsp_ram(0x0d, 0x40);
    return;

  // loc_2E7B8
  case 10:
    if (!x_dsp_mars) {
       dp_write_dsp_ram(0x0d, 0x70);
       return;
	}
    if (((byte_59EDE & 7) == 1) || ((byte_59EDE & 7) == 2)) {
       dp_write_dsp_ram(0x0d, 0x100);
       return;
	}
    dp_write_dsp_ram(0x0d, 0x70);
    return;

  // loc_2E7B1
  case 11:
    // Pavels dissamebly shows something _very_ strange!
	// My equivalent shows pushd 0130h followed by a jump
	// to the equivalent of 2E7FB.
    dp_write_dsp_ram(0x0d, 0x130);
    return;

  // loc_2E7AA
  case 12:
    // Pavels dissamebly shows something _very_ strange!
	// My equivalent shows pushd 0400h followed by a jump
	// to the equivalent of 2E7FB.
    dp_write_dsp_ram(0x0d, 0x4000);
    return;

  // loc_2e74e
  case 13:
    if ((byte_59EDF & 0x80) == 0x80) {
       dp_change_mercury_gain (0, 2, homol[0xf32-HBASE], (homol[0xf33-HBASE] | 1));
       return;
	}
    // else drop int code for 14.

  //loc_2e774
  case 14:
    if (x_dsp_mars) {
	  writebio(1, 0);
	  return;
	}
	writebio(0x40, 0);
	return;

  //loc_2e9e4
  case 15:
    if (byte_59F0B == 0)
      return;

    if (!CpqFlag)
      return;

    if (x_dsp_mars) {
      writebio(0x304, 0);
      return;
    }
    writebio(0x80, 0);
    return;

// 0002EB30                 dd offset loc_2EA07		16
  // Similar to 15 with minor difference! (, 1 -> , 0) */
  case 16:
    if (byte_59F0B == 0)
      return;

    if (!CpqFlag)
      return;

    if (x_dsp_mars) {
      writebio(0x304, 1);
      return;
    }
    writebio(0x80, 1);
    return;

// 0002EB34                 dd offset loc_2EA34		17
  case 17:
    writebio(0xffff, 0);

    if (!CpqFlag)
      return;

    writebio(0x302, 0);
    return;

// 0002EB38                 dd offset loc_2EA55		18
  case 18:
    writebio(0xffff, 1);

    if (!CpqFlag)
      return;

    writebio(0x302, 1);
    return;

  case 19: case 20: case 21: case 22:
    return;

  // loc_2e807
  case 23:
    if (x_dsp_mars)
       if (((byte_59EDE & 7) == 1) || ((byte_59EDE & 7) == 2)) {
		 //loc_2e820:
          if (word_59EE1 != 0x1179) return;
          writebio(0x1240, 0);
          return;
          }
    if (!x_dsp_mars) goto loc_2e87e;
       
    // What does this do? - see initialisation code.
    init_1027(1);

    // This looks like rubbish!
    if (!x_dsp_mars) goto loc_2e87e;
    
    writebio(0x1240, 0);
   
    if (CpqFlag) return;

    writebio(0x180, 0);
    return;

loc_2e87e:
    writebio(0xffff, 0);

    if (!CpqFlag) return;

    writebio(0x180, 0);
    return;

  // loc_2e89b
  case 24:
    if (x_dsp_mars)
       if (((byte_59EDE & 7) == 1) || ((byte_59EDE & 7) == 2)) {
		 //loc_2e820:
          if (word_59EE1 != 0x1179) goto loc_2E8D8;
          writebio(0x1240, 1);
		  goto loc_2E8D8;
          }

	if (x_dsp_mars)
	  writebio(0x1240, 1);
	else
	  writebio(0xffff, 1);

  loc_2E8D8:
	if (CpqFlag)  writebio(0x180, 1);

	if (x_dsp_mars)
	  if (((byte_59EDE & 7) == 1) || ((byte_59EDE & 7) == 2))
		return;

	if (x_dsp_mars) 
	  {
		dp_regandor (0xcb, 0xf3, 0);
		init_1027 (0);
	  }
	dp_regandor (0xcf, 0x3f, 0);
	dp_regwrite (0xda, 1);
	dp_regandor (0xcb, 0xff, 8);
	dp_modem_command_long (3, 0xd1, 0, 0xea, 0);
	return;

// loc_2EACF
  case 25:
    if (x_dsp_mars)
      writebio(0xffff, 1);
    else
      writebio(0x180, 1);
    return;

// loc_2EAC3
  case 26:
    if (x_dsp_mars)
      writebio(0xffff, 0);
    else
      writebio(0x180, 0);
    return;

  // loc_2EA72