;;  Copyright ARM Ltd 2002. All rights reserved.
;;
;;  This code provides basic global enable for an ARM92XT cache:
;;
;;  This code must be run from a privileged mode


        AREA   INIT92XCACHE, CODE, READONLY      ; name this block of code

        EXPORT core_init
core_init

;
; Set global core configurations
;===============================
;
        MRC     p15, 0, r0, c1, c0, 0       ; read CP15 register 1 into r0

        ORR     r0, r0, #(0x1  <<12)        ; enable I Cache
        ORR     r0, r0, #(0x1  <<2)         ; enable D Cache

        MCR     p15, 0, r0, c1, c0, 0       ; write CP15 register 1
        MOV     pc, lr

        END                                 ; mark the end of this file