;;  Copyright ARM Ltd 2002. All rights reserved.
;;
;;  This code initialises the TCMs before calling __main
;;  this allows scatter loading to relocate code into the TCMs
;;
;;  This code must be run from a privileged mode


Region_Enable  EQU 2_1

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled


        AREA   INIT946TCM, CODE, READONLY   ; name this block of code

        ENTRY

        IMPORT Data_TCM_Base


; if MMU/MPU enabled - disable (useful for ARMulator tests)
;
; Force core into known state - otherwise reload will fail!
;      
       MOV     r0, #0x78                    ;         
       MCR     p15, 0, r0, c1, c0, 0        ; write value back

       MOV     r0,#0                        ; disable any other regions
       MCR     p15, 0, r0, c6, c0, 0  
       MCR     p15, 0, r0, c6, c1, 0        ; only required if startup state unknown 
       MCR     p15, 0, r0, c6, c2, 0        
       MCR     p15, 0, r0, c6, c3, 0
       MCR     p15, 0, r0, c6, c4, 0
       MCR     p15, 0, r0, c6, c5, 0
       MCR     p15, 0, r0, c6, c6, 0
       MCR     p15, 0, r0, c6, c7, 0
       
       MCR     p15, 0, r0, c7, c5, 0        ; flush the I Cache
       MCR     p15, 0, r0, c7, c6, 0        ; flush the D Cache
        
       MCR     p15, 0, r0, c7, c10, 4       ; drain the write buffer
;
;

        IMPORT  top_of_stacks               ; defined in stack.s and located by scatter file
        LDR     SP, =top_of_stacks
        

;
;Next block sets the TCMs base and size registers to their actual size
;Note actual size should be contained in the register at reset.
;
;         
;;TCM Configuration 
;==================

        LDR     r0,=Data_TCM_Base           ; Read D-TCM Base - set by scatter file
        MRC     p15, 0, r1, c9, c1, 0       ; Read D-TCM
        ORR     r1, r1, r0
        MCR     p15, 0, r1, c9, c1, 0       ; Set Data D-TCM base
        
        
; I-TCM base fixed at 0x0 for ARM946E-S        

;
; Set global core configurations 
;===============================
;
        MRC     p15, 0, r0, c1, c0, 0       ; read CP15 register 1 into r0

 IF :DEF: TCM
        ORR     r0, r0, #(0x1 <<18)         ; enable I-TCM
        ORR     r0, r0, #(0x1 <<16)         ; enable D-TCM 
 ELSE 
        BIC     r0, r0, #(0x1 <<18)         ; Don't enable I-TCM
        BIC     r0, r0, #(0x1 <<16)         ; Don't enable D-TCM 
 ENDIF        

        MCR     p15, 0, r0, c1, c0, 0       ; write CP15 register 1
;
;
        IMPORT  Init_MPU                    ; Import label to MPU init code

        B       Init_MPU


        END