/* * Copyright (c) 1995 Mark Tinguely and Jim Lowe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software *    must display the following acknowledgement: *	This product includes software developed by Mark Tinguely and Jim Lowe * 4. The name of the author may not be used to endorse or promote products  *    derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. *//*		Change History:	8/21/95		Release	8/23/95		On advice from Stefan Esser, added volatile to PCI			memory pointers to remove PCI caching .	8/29/95		Fixes suggested by Bruce Evans.			meteor_mmap should return -1 on error rather than 0.			unit # > NMETEOR should be unit # >= NMETEOR.	10/24/95	Turn 50 Hz processing for SECAM and 60 Hz processing			off for AUTOMODE.	11/11/95	Change UV from always begin signed to ioctl selected			to either signed or unsigned.	12/07/95	Changed 7196 startup codes for 50 Hz as recommended			by Luigi Rizzo (luigi@iet.unipi.it)	12/08/95	Clear SECAM bit in PAL/NTSC and set input field count			bits for 50 Hz mode (PAL/SECAM) before I was setting the			output count bits. by Luigi Rizzo (luigi@iet.unipi.it)	12/18/95	Correct odd DMA field (never exceed, but good for safety			Changed 7196 startup codes for 50 Hz as recommended			by Luigi Rizzo (luigi@iet.unipi.it)	12/19/95	Changed field toggle mode to enable (offset 0x3c)			recommended by luigi@iet.unipi.it			Added in prototyping, include file, staticizing,			and DEVFS changes from FreeBSD team.			Changed the default allocated pages from 151 (NTSC)			to 217 (PAL).			Cleaned up some old comments in iic_write().			Added a Field (even or odd) only capture mode to 			eliminate the high frequency problems with compression			algorithms.  Recommended by luigi@iet.unipi.it.			Changed geometry ioctl so if it couldn't allocated a			large enough contiguous space, it wouldn't free the			stuff it already had.			Added new mode called YUV_422 which delivers the			data in planer Y followed by U followed by V. This			differs from the standard YUV_PACKED mode in that			the chrominance (UV) data is in the correct (different)			order. This is for programs like vic and mpeg_encode			so they don't have to reorder the chrominance data.			Added field count to stats.			Increment frame count stat if capturing continuous on			even frame grabs.			Added my email address to these comments			(james@cs.uwm.edu) suggested by (luigi@iet.unipt.it :-).			Changed the user mode signal mechanism to allow the			user program to be interrupted at the end of a frame			in any one of the modes.  Added SSIGNAL ioctl.			Added a SFPS/GFPS ioctl so one may set the frames per			second that the card catpures.  This code needs to be			completed.			Changed the interrupt routine so synchronous capture			will work on fields or frames and the starting frame			can be either even or odd.			Added HALT_N_FRAMES and CONT_N_FRAMES so one could			stop and continue synchronous capture mode.			Change the tsleep/wakeup function to wait on mtr			rather than &read_intr_wait.	1/22/96		Add option (METEOR_FreeBSD_210) for FreeBSD 2.1			to compile.			Changed intr so it only printed errors every 50 times.			Added unit number to error messages.			Added get_meteor_mem and enabled range checking.	1/30/96		Added prelim test stuff for direct video dma transfers			from Amancio Hasty (hasty@rah.star-gate.com).  Until			we get some stuff sorted out, this will be ifdef'ed			with METEOR_DIRECT_VIDEO.  This is very dangerous to			use at present since we don't check the address that			is passed by the user!!!!!	2/26/96		Added special SVIDEO input device type.	2/27/96		Added meteor_reg.h file and associate types Converted			meteor.c over to using meteor.h file.  Prompted by			Lars Jonas Olsson <ljo@po.cwru.edu>.	2/28/96		Added meteor RGB code from Lars Jonas Olsson			<ljo@po.cwru.edu>.  I make some mods to this code, so			I hope it still works as I don't have an rgb card to			test with.	2/29/96		<ljo@po.cwru.edu> tested the meteor RGB and supplied			me with diffs.  Thanks, we now have a working RGB			version of the driver.  Still need to clean up this			code.	3/1/96		Fixed a nasty little bug that was clearing the VTR			mode bit when the 7196 status was requested.	3/15/96		Fixed bug introduced in previous version that			stopped the only fields mode from working.			Added METEOR{GS}TS ioctl, still needs work.	3/25/96		Added YUV_9 and YUV_12 modes.  Cleaned up some of the			code and converted variables to use the new register			types.	4/8/96		Fixed the a bug in with the range enable.  Pointed			out by Jim Bray.	5/13/96		Fix the FPS ioctl so it actually sets the frames			per second.  Code supplied by ian@robots.ox.ac.uk.			The new code implements a new define:			METEOR_SYSTEM_DEFAULT  which should be defined as			METEOR_PAL, METEOR_SECAM, or METEOR_NTSC in your system			configuration file.  If METEOR_SYSTEM_DEFAULT isn't			defined, and there is not a signal when set_fps is			called, then the call has no effect.			Changed the spelling of PLANER to PLANAR as pointed			out by Paco Hope <paco@cs.virigina.edu> and define			PLANER to be PLANAR for backward compatibility.	5/28/95		METEOR_INPUT_DEV_RCA -> METEOR_INPUT_DEV0, not			METEOR_GEO_DEV0.  Pointed out by Ian Reid,			<ian@robots.ox.ac.uk>.			METEOR_DEV_MASK should be 0x0000f000 and not 			0x2000f000, otherwise METEOR_RGB gets masked			out.  Pointed out by Ian Reid.			Changed the fps code to give even distribution for			low frame rates.  Code supplied by Ian Reid.			Fix some problems with the RGB version.  Patch supplied			by <ljo@po.cwru.edu>.			Added METEOR_FIELD_MODE to include files for a 			future version of this driver.*/#include "meteor.h"#if NMETEOR > 0#include "opt_devfs.h"#include "opt_meteor.h"#include <sys/param.h>#include <sys/systm.h>#include <sys/conf.h>#include <sys/kernel.h>#include <sys/signalvar.h>#include <sys/mman.h>#ifdef DEVFS#include <sys/devfsext.h>#endif /* DEVFS */#include <sys/uio.h>#if defined(METEOR_FreeBSD_210)#include <machine/cpu.h>	/* bootverbose */#endif#include <vm/vm.h>#include <vm/vm_kern.h>#include <vm/pmap.h>#include <vm/vm_extern.h>#include "pci.h"#if NPCI > 0#include <pci/pcivar.h>#include <pci/pcireg.h>#endif#include <machine/ioctl_meteor.h>#include <pci/meteor_reg.h>static void meteor_intr __P((void *arg));/*  * Allocate enough memory for: *	768x576 RGB 16 or YUV (16 storage bits/pixel) = 884736 = 216 pages * * You may override this using the options "METEOR_ALLOC_PAGES=value" in your * kernel configuration file. */#ifndef METEOR_ALLOC_PAGES#define METEOR_ALLOC_PAGES 217#endif#define METEOR_ALLOC (METEOR_ALLOC_PAGES * PAGE_SIZE)static meteor_reg_t meteor[NMETEOR];#define METEOR_NUM(mtr)	((mtr - &meteor[0])/sizeof(meteor_reg_t))#define METPRI (PZERO+8)|PCATCHstatic	const char*	met_probe (pcici_t tag, pcidi_t type);static	void	met_attach(pcici_t tag, int unit);static	u_long	met_count;static struct	pci_device met_device = {	"meteor",	met_probe,	met_attach,	&met_count};DATA_SET (pcidevice_set, met_device);#if defined(METEOR_FreeBSD_210)	/* XXX */d_open_t	meteor_open;d_close_t	meteor_close;d_read_t	meteor_read;d_write_t	meteor_write;d_ioctl_t	meteor_ioctl;d_mmap_t	meteor_mmap;#elsestatic	d_open_t	meteor_open;static	d_close_t	meteor_close;static	d_read_t	meteor_read;static	d_write_t	meteor_write;static	d_ioctl_t	meteor_ioctl;static	d_mmap_t	meteor_mmap;#define CDEV_MAJOR 67static struct cdevsw meteor_cdevsw =         { meteor_open,  meteor_close,   meteor_read,    meteor_write,   /*67*/          meteor_ioctl, nostop,         nullreset,   nodevtotty,/* Meteor */          seltrue,	meteor_mmap, NULL,	"meteor",	NULL,	-1 };#endifstatic mreg_t saa7116_pci_default[sizeof(struct saa7116_regs)/sizeof(mreg_t)]={				/* PCI Memory registers	    	*/				/* BITS	  Type	Description	*//* 0x00 */	0x00000000,	/* 31:1   e*RW	DMA 1 (Even)				      0   RO    0x0 		*//* 0x04 */	0x00000000,	/* 31:2   e*RW	DMA 2 (Even)				    1:0   RO	0x0		*//* 0x08 */	0x00000000,	/* 31:2   e*RW  DMA 3 (Even)				    1:0   RO    0x0		*//* 0x0c */	0x00000000,	/* 31:1   o*RW	DMA 1 (Odd)				      0   RO	0x0		*//* 0x10 */	0x00000000,	/* 31:2	  o*RW	DMA 2 (Odd)				    1:0	  RO	0x0		*//* 0x14 */	0x00000000,	/* 31:2   o*RW	DMA 3 (Odd)				    1:0   RO	0x0		*//* 0x18 */	0x00000500,	/* 15:2   e*RW  Stride 1 (Even)				    1:0   RO	0x0		*//* 0x1c */	0x00000000,	/* 15:2	  e*RW	Stride 2 (Even)				    1:0	  RO	0x0		*//* 0x20 */	0x00000000,	/* 15:2	  e*RW	Stride 3 (Even)				    1:0	  RO	0x0		*//* 0x24 */	0x00000500,	/* 15:2	  o*RW	Stride 1 (Odd)				    1:0	  RO	0x0		*//* 0x28 */	0x00000000,	/* 15:2	  o*RW	Stride 2 (Odd)				    1:0	  RO	0x0		*//* 0x2c */	0x00000000,	/* 15:2	  o*RW	Stride 3 (Odd)				    1:0	  RO	0x0		*//* 0x30 */	0xeeeeee01,	/* 31:8	  *RW	Route (Even)				    7:0	  *RW	Mode (Even)	*//* 0x34 */	0xeeeeee01,	/* 31:8	  *RW	Route (Odd)				    7:0	  *RW	Mode (Odd)	*//* 0x38 */	0x00200020, 	/* 22:16  *RW	FIFO Trigger Planer Mode,				    6:0	  *RW	FIFO Trigger Packed Mode *//* 0x3c */	0x00000107,	/*  9:8   *RW	Reserved (0x0)				      2	  *RW	Field Toggle				      1	  *RW	Reserved (0x1)				      0	  *RW	Reserved (0x1)		*//* 0x40 */	0x000000c0,	/*    15  *RW	Range Enable				      14  *RW	Corrupt Disable				      11  *RR	Address Error (Odd)				      10  *RR	Address Error (Even)				      9   *RR	Field Corrupt (Odd)				      8   *RR	Field Corrupt (Even)				      7	  *RW	Fifo Enable				      6   *RW	VRSTN#				      5	  *RR	Field Done (Odd)				      4   *RR	Field Done (Even)				      3	  *RS	Single Field Capture (Odd)				      2	  *RS	Single Field Capture (Even)				      1	  *RW	Capture (ODD) Continous				      0	  *RW	Capture (Even) Continous *//* 0x44 */	0x00000000,	/*  7:0	  *RW	Retry Wait Counter *//* 0x48 */	0x00000307,	/*    10  *RW	Interrupt mask, start of field				      9   *RW	Interrupt mask, end odd field				      8	  *RW	Interrupt mask, end even field				      2   *RR	Interrupt status, start of field				      1   *RR	Interrupt status, end of odd				      0	  *RR	Interrupt status, end of even *//* 0x4c */	0x00000001,	/* 31:0   *RW	Field Mask (Even) continous *//* 0x50 */	0x00000001,	/* 31:0   *RW	Field Mask (Odd) continous *//* 0x54 */	0x00000000,	/* 20:16  *RW	Mask Length (Odd)				    4:0	  *RW	Mask Length (Even)	*//* 0x58 */	0x0005007c,	/* 22:16  *RW	FIFO almost empty				    6:0	  *RW	FIFO almost full	*//* 0x5c */	0x461e1e0f,	/* 31:24  *RW	I2C Phase 4				   23:16  *RW	I2C Phase 3				   15:8   *RW	I2C Phase 2				    7:0	  *RW	I2C Phase 1	*//* 0x60 */	0x00000300,	/* 31:24  *RO	I2C Read Data				   23:16  **RW  I2C Auto Address				      11  RO	I2C SCL Input				      10  RO	I2C SDA Input				      9	  RR	I2C Direct Abort				      8   RR	I2C Auto Abort				      3   RW	I2C SCL Output				      2   RW	I2C SDA Output				      1	  RW	I2C Bypass				      0	  RW	I2C Auto Enable	*//* 0x64 */	0x00000000,	/*    24  RS	I2C New Cycle				   23:16  **RW	I2C Direct Address				   15:8   **RW	I2C Direct Sub-address				    7:0	  **RW	I2C Direct Write Address *//* 0x68 */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 1 (Even)				   23:16  **RW  I2C Auto Data 1 (Even)				   15:8   **RW  I2C Auto Sub-address 0 (Even)				    7:0	  **RW	I2C Auto Data 0 (Even) *//* 0x6c */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 3 (Even)				   23:16  **RW  I2C Auto Data 3 (Even)				   15:8   **RW  I2C Auto Sub-address 2 (Even)				    7:0	  **RW	I2C Auto Data 2 (Even) *//* 0x70 */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 5 (Even)				   23:16  **RW  I2C Auto Data 5 (Even)				   15:8   **RW  I2C Auto Sub-address 4 (Even)				    7:0	  **RW	I2C Auto Data 4 (Even) *//* 0x74 */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 7 (Even)				   23:16  **RW  I2C Auto Data 7 (Even)				   15:8   **RW  I2C Auto Sub-address 6 (Even)				    7:0	  **RW	I2C Auto Data 6 (Even) *//* 0x78 */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 1 (Odd)				   23:16  **RW  I2C Auto Data 1 (Odd)				   15:8   **RW  I2C Auto Sub-address 0 (Odd)				    7:0	  **RW	I2C Auto Data 0 (Odd) *//* 0x7c */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 3 (Odd)				   23:16  **RW  I2C Auto Data 3 (Odd)				   15:8   **RW  I2C Auto Sub-address 2 (Odd)				    7:0	  **RW	I2C Auto Data 2 (Odd) *//* 0x80 */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 5 (Odd)				   23:16  **RW  I2C Auto Data 5 (Odd)				   15:8   **RW  I2C Auto Sub-address 4 (Odd)				    7:0	  **RW	I2C Auto Data 4 (Odd) *//* 0x84 */	0x00000000,	/* 31:24  **RW  I2C Auto Sub-address 7 (Odd)				   23:16  **RW  I2C Auto Data 7 (Odd)				   15:8   **RW  I2C Auto Sub-address 6 (Odd)				    7:0	  **RW	I2C Auto Data 6 (Odd) *//* 0x88 */	0x00000000,	/* 23:16  **RW	I2C Register Enable (Odd)				    7:0	  **RW	I2C Register Enable (Even) *//* 0x8c */	0x00000000,	/* 23:2	  e*RW	DMA End (Even)				    1:0	  RO	0x0	*//* 0x90 */	0x00000000	/* 23:2	  e*RW	DMA End (Odd)				    1:0	  RO	0x0	*/};static u_char saa7196_i2c_default[NUM_SAA7196_I2C_REGS] = {			/* SAA7196 I2C bus control			*/			/* BITS	Function				*//* 00 */	0x50,	/* 7:0	Increment Delay				*//* 01 */	0x30,	/* 7:0	Horizontal Sync Begin for 50hz		*//* 02 */	0x00,	/* 7:0	Horizontal Sync Stop for 50hz		*//* 03 */	0xe8,	/* 7:0	Horizontal Sync Clamp Start for 50hz	*//* 04 */	0xb6,	/* 7:0	Horizontal Sync Clamp Stop for 50hz 	*//* 05 */	0xf4,	/* 7:0	Horizontal Sync Start after PH1 for 50hz *//* 06 */	0x46,	/*   7	Input mode =0 CVBS, =1 S-Video 			     6	Pre filter			   5:4  Aperture Bandpass characteristics			   3:2	Coring range for high freq			   1:0	Aperture bandpass filter weights	*//* 07 */	0x00,	/* 7:0	Hue					*//* 08 */	0x7f,	/* 7:3	Colour-killer threshold QAM (PAL, NTSC) *//* 09 */	0x7f,	/* 7:3	Colour-killer threshold SECAM		*//* 0a */	0x7f,	/* 7:0	PAL switch sensitivity			*//* 0b */	0x7f,	/* 7:0	SECAM switch sensitivity		*//* 0c */	0x40,	/*   7	Colour-on bit			   6:5	AGC filter				*//* 0d */	0x84,	/*   7	VTR/TV mode bit = 1->VTR mode			     3	Realtime output mode select bit			     2	HREF position select			     1	Status byte select			     0	SECAM mode bit				*//* 0e */	0x38,	/*   7	Horizontal clock PLL			     5	Select interal/external clock source			     4	Output enable of Horizontal/Vertical sync			     3	Data output YUV enable			     2	S-VHS bit			     1	GPSW2			     0	GPSW1					*//* 0f */	0x50,	/*   7	Automatic Field detection			     6	Field Select 0 = 50hz, 1=60hz			     5	SECAM cross-colour reduction			     4	Enable sync and clamping pulse			   3:1	Luminance delay compensation		*//* 10 */	0x00,	/*   2	Select HREF Position			   1:0  Vertical noise reduction		*//* 11 */	0x2c,	/* 7:0	Chrominance gain conrtol for QAM	*//* 12 */	0x40,	/* 7:0	Chrominance saturation control for VRAM port *//* 13 */	0x40,	/* 7:0	Luminance contract control for VRAM port *//* 14 */	0x34,	/* 7:0	Horizontal sync begin for 60hz		*/#ifdef notdef/* 15 */	0x0c,	/* 7:0	Horizontal sync stop for 60hz		*//* 16 */	0xfb,	/* 7:0	Horizontal clamp begin for 60hz		*//* 17 */	0xd4,	/* 7:0	Horizontal clamp stop for 60hz		*//* 18 */	0xec,	/* 7:0	Horizontal sync start after PH1 for 60hz */#else		0x0a, 0xf4, 0xce, 0xf4,#endif/* 19 */	0x80,	/* 7:0	Luminance brightness control for VRAM port *//* 1a */	0x00,/* 1b */	0x00,/* 1c */	0x00,/* 1d */	0x00,/* 1e */	0x00,/* 1f */	0x00,/* 20 */	0x90,	/*   7	ROM table bypass switch			   6:5	Set output field mode			     4	VRAM port outputs enable			   3:2	First pixel position in VRO data			   1:0	FIFO output register select		*/