/* $Id: ispreg.h,v 1.4.2.1 1999/05/11 05:51:39 mjacob Exp $ *//* release_5_11_99 *//* * Machine Independent (well, as best as possible) register * definitions for Qlogic ISP SCSI adapters. * *--------------------------------------- * Copyright (c) 1997 by Matthew Jacob * NASA/Ames Research Center * All rights reserved. *--------------------------------------- * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice immediately at the beginning of the file, without modification, *    this list of conditions, and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products *    derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */#ifndef	_ISPREG_H#define	_ISPREG_H/* * Hardware definitions for the Qlogic ISP  registers. *//* * This defines types of access to various registers. * *  	R:		Read Only *	W:		Write Only *	RW:		Read/Write * *	R*, W*, RW*:	Read Only, Write Only, Read/Write, but only *			if RISC processor in ISP is paused. *//* * Offsets for various register blocks. * * Sad but true, different architectures have different offsets. * * Don't be alarmed if none of this makes sense. The original register * layout set some defines in a certain pattern. Everything else has been * grafted on since. For example, the ISP1080 manual will state that DMA * registers start at 0x80 from the base of the register address space. * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 * to start at offset 0x60 because the DMA registers are all defined to * be DMA_BLOCK+0x20 and so on. Clear? */#define	BIU_REGS_OFF			0x00#define	PCI_MBOX_REGS_OFF		0x70#define	PCI_MBOX_REGS2100_OFF		0x10#define	SBUS_MBOX_REGS_OFF		0x80#define	PCI_SXP_REGS_OFF		0x80#define	SBUS_SXP_REGS_OFF		0x200#define	PCI_RISC_REGS_OFF		0x80#define	SBUS_RISC_REGS_OFF		0x400/* Bless me! Chip designers have putzed it again! */#define	ISP1080_DMA_REGS_OFF		0x60#define	DMA_REGS_OFF			0x00	/* same as BIU block *//* * NB:	The *_BLOCK definitions have no specific hardware meaning. *	They serve simply to note to the MD layer which block of *	registers offsets are being accessed. */#define	_NREG_BLKS	5#define	_BLK_REG_SHFT	13#define	_BLK_REG_MASK	(7 << _BLK_REG_SHFT)#define	BIU_BLOCK	(0 << _BLK_REG_SHFT)#define	MBOX_BLOCK	(1 << _BLK_REG_SHFT)#define	SXP_BLOCK	(2 << _BLK_REG_SHFT)#define	RISC_BLOCK	(3 << _BLK_REG_SHFT)#define	DMA_BLOCK	(4 << _BLK_REG_SHFT)/* * Bus Interface Block Register Offsets */#define	BIU_ID_LO	BIU_BLOCK+0x0	/* R  : Bus ID, Low */#define		BIU2100_FLASH_ADDR	BIU_BLOCK+0x0#define	BIU_ID_HI	BIU_BLOCK+0x2	/* R  : Bus ID, High */#define		BIU2100_FLASH_DATA	BIU_BLOCK+0x2#define	BIU_CONF0	BIU_BLOCK+0x4	/* R  : Bus Configuration #0 */#define	BIU_CONF1	BIU_BLOCK+0x6	/* R  : Bus Configuration #1 */#define		BIU2100_CSR		BIU_BLOCK+0x6#define	BIU_ICR		BIU_BLOCK+0x8	/* RW : Bus Interface Ctrl */#define	BIU_ISR		BIU_BLOCK+0xA	/* R  : Bus Interface Status */#define	BIU_SEMA	BIU_BLOCK+0xC	/* RW : Bus Semaphore */#define	BIU_NVRAM	BIU_BLOCK+0xE	/* RW : Bus NVRAM */#define	DFIFO_COMMAND	BIU_BLOCK+0x60	/* RW : Command FIFO Port */#define		RDMA2100_CONTROL	DFIFO_COMMAND#define	DFIFO_DATA	BIU_BLOCK+0x62	/* RW : Data FIFO Port *//* * Putzed DMA register layouts. */#define	CDMA_CONF	DMA_BLOCK+0x20	/* RW*: DMA Configuration */#define		CDMA2100_CONTROL	CDMA_CONF#define	CDMA_CONTROL	DMA_BLOCK+0x22	/* RW*: DMA Control */#define	CDMA_STATUS 	DMA_BLOCK+0x24	/* R  : DMA Status */#define	CDMA_FIFO_STS	DMA_BLOCK+0x26	/* R  : DMA FIFO Status */#define	CDMA_COUNT	DMA_BLOCK+0x28	/* RW*: DMA Transfer Count */#define	CDMA_ADDR0	DMA_BLOCK+0x2C	/* RW*: DMA Address, Word 0 */#define	CDMA_ADDR1	DMA_BLOCK+0x2E	/* RW*: DMA Address, Word 1 */#define	CDMA_ADDR2	DMA_BLOCK+0x30	/* RW*: DMA Address, Word 2 */#define	CDMA_ADDR3	DMA_BLOCK+0x32	/* RW*: DMA Address, Word 3 */#define	DDMA_CONF	DMA_BLOCK+0x40	/* RW*: DMA Configuration */#define		TDMA2100_CONTROL	DDMA_CONF#define	DDMA_CONTROL	DMA_BLOCK+0x42	/* RW*: DMA Control */#define	DDMA_STATUS	DMA_BLOCK+0x44	/* R  : DMA Status */#define	DDMA_FIFO_STS	DMA_BLOCK+0x46	/* R  : DMA FIFO Status */#define	DDMA_COUNT_LO	DMA_BLOCK+0x48	/* RW*: DMA Xfer Count, Low */#define	DDMA_COUNT_HI	DMA_BLOCK+0x4A	/* RW*: DMA Xfer Count, High */#define	DDMA_ADDR0	DMA_BLOCK+0x4C	/* RW*: DMA Address, Word 0 */#define	DDMA_ADDR1	DMA_BLOCK+0x4E	/* RW*: DMA Address, Word 1 *//* these are for the 1040A cards */#define	DDMA_ADDR2	DMA_BLOCK+0x50	/* RW*: DMA Address, Word 2 */#define	DDMA_ADDR3	DMA_BLOCK+0x52	/* RW*: DMA Address, Word 3 *//* * Bus Interface Block Register Definitions *//* BUS CONFIGURATION REGISTER #0 */#define	BIU_CONF0_HW_MASK		0x000F	/* Hardware revision mask *//* BUS CONFIGURATION REGISTER #1 */#define	BIU_SBUS_CONF1_PARITY		0x0100 	/* Enable parity checking */#define	BIU_SBUS_CONF1_FCODE_MASK	0x00F0	/* Fcode cycle mask */#define	BIU_PCI_CONF1_FIFO_128		0x0040	/* 128 bytes FIFO threshold */#define	BIU_PCI_CONF1_FIFO_64		0x0030	/* 64 bytes FIFO threshold */#define	BIU_PCI_CONF1_FIFO_32		0x0020	/* 32 bytes FIFO threshold */#define	BIU_PCI_CONF1_FIFO_16		0x0010	/* 16 bytes FIFO threshold */#define	BIU_BURST_ENABLE		0x0004	/* Global enable Bus bursts */#define	BIU_SBUS_CONF1_FIFO_64		0x0003	/* 64 bytes FIFO threshold */#define	BIU_SBUS_CONF1_FIFO_32		0x0002	/* 32 bytes FIFO threshold */#define	BIU_SBUS_CONF1_FIFO_16		0x0001	/* 16 bytes FIFO threshold */#define	BIU_SBUS_CONF1_FIFO_8		0x0000	/* 8 bytes FIFO threshold */#define	BIU_SBUS_CONF1_BURST8		0x0008 	/* Enable 8-byte  bursts */#define	BIU_PCI_CONF1_SXP		0x0008	/* SXP register select */#define	BIU_PCI1080_CONF1_SXP		0x0100	/* SXP bank select */#define	BIU_PCI1080_CONF1_DMA		0x0300	/* DMA bank select *//* ISP2100 Bus Control/Status Register */#define	BIU2100_ICSR_REGBSEL		0x30	/* RW: register bank select */#define		BIU2100_RISC_REGS	(0 << 4)	/* RISC Regs */#define		BIU2100_FB_REGS		(1 << 4)	/* FrameBuffer Regs */#define		BIU2100_FPM0_REGS	(2 << 4)	/* FPM 0 Regs */#define		BIU2100_FPM1_REGS	(3 << 4)	/* FPM 1 Regs */#define	BIU2100_PCI64			0x04	/*  R: 64 Bit PCI slot */#define	BIU2100_FLASH_ENABLE		0x02	/* RW: Enable Flash RAM */#define	BIU2100_SOFT_RESET		0x01/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR *//* BUS CONTROL REGISTER */#define	BIU_ICR_ENABLE_DMA_INT		0x0020	/* Enable DMA interrupts */#define	BIU_ICR_ENABLE_CDMA_INT		0x0010	/* Enable CDMA interrupts */#define	BIU_ICR_ENABLE_SXP_INT		0x0008	/* Enable SXP interrupts */#define	BIU_ICR_ENABLE_RISC_INT		0x0004	/* Enable Risc interrupts */#define	BIU_ICR_ENABLE_ALL_INTS		0x0002	/* Global enable all inter */#define	BIU_ICR_SOFT_RESET		0x0001	/* Soft Reset of ISP */#define	BIU2100_ICR_ENABLE_ALL_INTS	0x8000#define	BIU2100_ICR_ENA_FPM_INT		0x0020#define	BIU2100_ICR_ENA_FB_INT		0x0010#define	BIU2100_ICR_ENA_RISC_INT	0x0008#define	BIU2100_ICR_ENA_CDMA_INT	0x0004#define	BIU2100_ICR_ENABLE_RXDMA_INT	0x0002#define	BIU2100_ICR_ENABLE_TXDMA_INT	0x0001#define	BIU2100_ICR_DISABLE_ALL_INTS	0x0000#define	ENABLE_INTS(isp)	(IS_SCSI(isp))?  \ ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS)#define	INTS_ENABLED(isp)	((IS_SCSI(isp))?  \ (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ (ISP_READ(isp, BIU_ICR) & \	(BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)))#define	DISABLE_INTS(isp)	ISP_WRITE(isp, BIU_ICR, 0)/* BUS STATUS REGISTER */#define	BIU_ISR_DMA_INT			0x0020	/* DMA interrupt pending */#define	BIU_ISR_CDMA_INT		0x0010	/* CDMA interrupt pending */#define	BIU_ISR_SXP_INT			0x0008	/* SXP interrupt pending */#define	BIU_ISR_RISC_INT		0x0004	/* Risc interrupt pending */#define	BIU_ISR_IPEND			0x0002	/* Global interrupt pending */#define	BIU2100_ISR_INT_PENDING		0x8000	/* Global interrupt pending */#define	BIU2100_ISR_FPM_INT		0x0020	/* FPM interrupt pending */#define	BIU2100_ISR_FB_INT		0x0010	/* FB interrupt pending */#define	BIU2100_ISR_RISC_INT		0x0008	/* Risc interrupt pending */#define	BIU2100_ISR_CDMA_INT		0x0004	/* CDMA interrupt pending */#define	BIU2100_ISR_RXDMA_INT_PENDING	0x0002	/* Global interrupt pending */#define	BIU2100_ISR_TXDMA_INT_PENDING	0x0001	/* Global interrupt pending *//* BUS SEMAPHORE REGISTER */#define	BIU_SEMA_STATUS		0x0002	/* Semaphore Status Bit */#define	BIU_SEMA_LOCK  		0x0001	/* Semaphore Lock Bit *//* NVRAM SEMAPHORE REGISTER */#define	BIU_NVRAM_CLOCK		0x0001#define	BIU_NVRAM_SELECT	0x0002#define	BIU_NVRAM_DATAOUT	0x0004#define	BIU_NVRAM_DATAIN	0x0008#define		ISP_NVRAM_READ		6/* COMNMAND && DATA DMA CONFIGURATION REGISTER */#define	DMA_ENABLE_SXP_DMA		0x0008	/* Enable SXP to DMA Data */#define	DMA_ENABLE_INTS			0x0004	/* Enable interrupts to RISC */#define	DMA_ENABLE_BURST		0x0002	/* Enable Bus burst trans */#define	DMA_DMA_DIRECTION		0x0001	/*						 * Set DMA direction:						 *	0 - DMA FIFO to host						 *	1 - Host to DMA FIFO						 *//* COMMAND && DATA DMA CONTROL REGISTER */#define	DMA_CNTRL_SUSPEND_CHAN		0x0010	/* Suspend DMA transfer */#define	DMA_CNTRL_CLEAR_CHAN		0x0008	/*						 * Clear FIFO and DMA Channel,						 * reset DMA registers						 */#define	DMA_CNTRL_CLEAR_FIFO		0x0004	/* Clear DMA FIFO */#define	DMA_CNTRL_RESET_INT		0x0002	/* Clear DMA interrupt */#define	DMA_CNTRL_STROBE		0x0001	/* Start DMA transfer *//* * Variants of same for 2100 */#define	DMA_CNTRL2100_CLEAR_CHAN	0x0004#define	DMA_CNTRL2100_RESET_INT		0x0002/* DMA STATUS REGISTER */#define	DMA_SBUS_STATUS_PIPE_MASK	0x00C0	/* DMA Pipeline status mask */#define	DMA_SBUS_STATUS_CHAN_MASK	0x0030	/* Channel status mask */#define	DMA_SBUS_STATUS_BUS_PARITY	0x0008	/* Parity Error on bus */#define	DMA_SBUS_STATUS_BUS_ERR		0x0004	/* Error Detected on bus */#define	DMA_SBUS_STATUS_TERM_COUNT	0x0002	/* DMA Transfer Completed */#define	DMA_SBUS_STATUS_INTERRUPT	0x0001	/* Enable DMA channel inter */#define	DMA_PCI_STATUS_INTERRUPT	0x8000	/* Enable DMA channel inter */#define	DMA_PCI_STATUS_RETRY_STAT	0x4000	/* Retry status */#define	DMA_PCI_STATUS_CHAN_MASK	0x3000	/* Channel status mask */#define	DMA_PCI_STATUS_FIFO_OVR		0x0100	/* DMA FIFO overrun cond */#define	DMA_PCI_STATUS_FIFO_UDR		0x0080	/* DMA FIFO underrun cond */#define	DMA_PCI_STATUS_BUS_ERR		0x0040	/* Error Detected on bus */#define	DMA_PCI_STATUS_BUS_PARITY	0x0020	/* Parity Error on bus */#define	DMA_PCI_STATUS_CLR_PEND		0x0010	/* DMA clear pending */#define	DMA_PCI_STATUS_TERM_COUNT	0x0008	/* DMA Transfer Completed */