?? mcu_drv.h
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/*_____ D E C L A R A T I O N ______________________________________________*/
/*--------------------------- SYSTEM MANAGEMENT -----------------------*/
#define Disable_ale() (AUXR |= MSK_AO)
#define Enable_ale() (AUXR &= ~MSK_AO)
#define Switch_ale() (AUXR ^= MSK_AO)
/*--------------------------- CLOCK TREE -----------------------*/
#define Set_x2_mode() Set_cpu_8mhz_osc()
#define Set_x1_mode() Set_cpu_4mhz_osc()
#define Mode_x2() ((CKCON & MSK_X2) == MSK_X2)
#define Set_cpu_pll(bckrl) (CKCON0 &= ~0x01, CKRL= bckrl, CKSEL |= 0x01)
#define Set_cpu_24mhz_pll() (CKCON0 &= ~0x01, CKRL= 0x0E, CKSEL |= 0x01)
#define Set_cpu_16mhz_pll() (CKCON0 &= ~0x01, CKRL= 0X0D, CKSEL |= 0x01)
#define Set_cpu_12mhz_pll() (CKCON0 &= ~0x01, CKRL= 0x0C, CKSEL |= 0x01)
#define Set_cpu_9_6mhz_pll() (CKCON0 &= ~0x01, CKRL= 0x0B, CKSEL |= 0x01)
#define Set_cpu_8mhz_pll() (CKCON0 &= ~0x01, CKRL= 0x0A, CKSEL |= 0x01)
#define Set_cpu_osc(bckrl) (CKSEL &= ~0x01, CKCON0 &= ~0x01, CKRL=bckrl)
#define Set_cpu_8mhz_osc() (CKSEL &= ~0x01, CKCON0 |= 0x01)
#define Set_cpu_4mhz_osc() (CKSEL &= ~0x01, CKCON0 &= ~0x01, CKRL=0x0F)
#define Set_pll_96mhz() (PLLDIV=0xB0)
#define Enable_pll() (PLLCON |= 0x02)
#define Disable_pll() (PLLCON &= ~0x02)
#define Lock_pll() while(!(PLLCON & 0x01))
//Bug in previous versions : the instruction While(PLLCON & 0x01)
//does not work because PLL is considered as LOCKED when PLLCON.0=1
#define Test_pll_for_cpu() (CKSEL & 0x01)
#define Select_osc_for_cpu() (CKSEL &= ~0x01)
#define Select_pll_for_cpu() (CKSEL |= 0x01)
#define Select_xtal48_for_scib_usb() (PLLCON |= 0x04)
#define Select_xtal8_for_scib() (PLLCON |= 0x04)
#define Select_pll_for_scib_usb() (PLLCON &= ~0x04)
#define Set_scib_clk(x) (SCSR|=0x01, SCICLK=x, PLLCON &= ~0x04)
#define Set_scib_4mhz_pll() (SCSR|=0x01, SCICLK=0x24, PLLCON &= ~0x04)
#define Set_scib_4_8mhz_pll() (SCSR|=0x01, SCICLK=0x26, PLLCON &= ~0x04)
#define Set_scib_4mhz_xtal8() (PLLCON |= 0x04, SCSR|=0x01, SCICLK=0x2F)
/* --- CLOCK TREE MACRO ---*/
#define CPU_PLL 0 /* init CPU on PLL clock */
#define CPU_OSC 1 /* init CPU on OSC clock */
#define PLL 0 /* init CPU on PLL clock */
#define OSC 1 /* init CPU on OSC clock */
#define X1 0
#define X2 1
#define Set_cpu_clock(CPU_FREQ, CLOCK_SOURCE, CPU_MODE) \
//CPU_FREQ (Hz) = Quartz frequency or \
// Equivalent Oscillator Frequency if PR1<>1/2 \
//CLOCK_SOURCE = PLL | OSC \
//CPU_MODE = X1 | X2 \
{ \
if (CLOCK_SOURCE == PLL) \
{ \
Set_cpu_pll(16-48000000/(CPU_FREQ/2)); \
} \
else \
{ \
if (CPU_MODE == X2) {Set_cpu_8mhz_osc();} \
else {Set_cpu_osc(16-4000000/(CPU_FREQ/2));} \
} \
}
/*--------------------------- POWER MANGEMENT -------------------------*/
#define Set_idle_mode() (PCON |= MSK_IDLE)
////////////////////////////////////////////////////////////////////////
//BUG#152 : Power down exit failure in X2 mode.
//If CPU is configured in X2 mode when exiting from power down mode,
//the fist address fetched may be lost
//WORKAROUNDS : use one or both following workarounds
//a) add a NOP instruction just after the instruction which activates
//the power down mode
//b) set the CPU in X1 mode before entering in power down mode
#define Set_power_down_mode() (PCON |= MSK_PD,_nop_()/*,ACC=~ACC*/)
////////////////////////////////////////////////////////////////////////
#define Clear_pof_bit() (PCON &= ~MSK_PCON_POF)
#define Set_pof_bit() (PCON |= MSK_PCON_POF)
#define Test_pof() (PCON & MSK_PCON_POF)
/*--------------------------- MEMORY CONTROLLER -----------------------*/
#define Enable_eram() (AUXR &= ~MSK_EXTRAM)
#define Disable_eram() (AUXR |= MSK_EXTRAM)
#define Set_eram_size(s) ((AUXR &= ~MSK_XRS),(AUXR |= s))
#define Map_internal_xram_256() Set_eram_size(ERAM_256)
#define Map_internal_xram_512() Set_eram_size(ERAM_512)
/*--------------------------- INTERRUPTIONS ---------------------------*/
#define Enable_all_interrupts() (EA = 1)
#define Disable_all_interrupts() (EA = 0)
#define Set_kbd_int_prio_lev0() (IPH1 &= ~MSK_IPH1_PKBH, IPL1 &= ~MSK_IPL1_PKBL)
#define Set_kbd_int_prio_lev1() (IPH1 &= ~MSK_IPH1_PKBH, IPL1 |= MSK_IPL1_PKBL)
#define Set_kbd_int_prio_lev2() (IPH1 |= MSK_IPH1_PKBH, IPL1 &= ~MSK_IPL1_PKBL)
#define Set_kbd_int_prio_lev3() (IPH1 |= MSK_IPH1_PKBH, IPL1 |= MSK_IPL1_PKBL)
#define Set_sci_int_prio_lev0() (IPH1 &= ~MSK_IPH1_PSCIH, IPL1 &= ~MSK_IPL1_PSCIL)
#define Set_sci_int_prio_lev1() (IPH1 &= ~MSK_IPH1_PSCIH, IPL1 |= MSK_IPL1_PSCIL)
#define Set_sci_int_prio_lev2() (IPH1 |= MSK_IPH1_PSCIH, IPL1 &= ~MSK_IPL1_PSCIL)
#define Set_sci_int_prio_lev3() (IPH1 |= MSK_IPH1_PSCIH, IPL1 |= MSK_IPL1_PSCIL)
#define Enable_kbd_int() (IEN1 |= MSK_IEN1_EKB )
#define Disable_kbd_int() (IEN1 &= ~MSK_IEN1_EKB)
#define Enable_spi_it() (IEN1 |= MSK_IEN1_ESPI)
/*----------------------------- UART ----------------------------------*/
#define Set_uart_x1_mode() (CKCON |= MSK_UARTX2)
#define Set_uart_x2_mode() (CKCON &=~MSK_UARTX2)
#define Uart_hw_init(config) (SCON=(config))
//#define Uart_set_baudrate(bdr) defined in /lib_mcu/uart/uart_bdr.h
#define Uart_enable() (SCON|=MSK_UART_ENABLE_RX|MSK_UART_TX_READY)
#define Uart_tx_ready() ((const bit)TI)
#define Uart_set_tx_busy() (TI=0)
#define Uart_send_byte(ch) (SBUF=ch)
#define Uart_rx_ready() ((const bit)RI)
#define Uart_get_byte() ((const char)SBUF)
#define Uart_ack_rx_byte() (RI=0)
/*--------------------------- WATCHDOG --------------------------------*/
#define Enable_watchdog() (WDTRST=0x1E,WDTRST=0xE1)
/*--------------------------- SPI------------ --------------------------*/
/*--------------------------- LEDS CONTROLLER --------------------------*/
#define Disable_all_leds() (LEDCON0 = 0x00, LEDCON1 = 0x00)
#define Led_all_off() (P3 |= 0xD4, P4 |= 0x38)
#define Led_all_on() (P3 &= ~0xD4, P4 &= ~0x38)
#define Led_all_2ma() (PMOD0&=~0xC0,PMOD1&=~0x03,LEDCON0=0x55,LEDCON1=0x55)
#define Led_all_4ma() (PMOD0&=~0xC0,PMOD1&=~0x03,LEDCON0=0xAA,LEDCON1=0xAA)
#define Led_all_10ma() (PMOD0&=~0xC0,PMOD1&=~0x03,LEDCON0=0xFF,LEDCON1=0xFF)
#define Disable_led0() /*P3.2*/(LEDCON0 &= ~0x03)
#define Set_led0_2ma() (PMOD0&=~0xC0,LEDCON0 |= 0x01,LEDCON0 &= ~0x02)
#define Set_led0_4ma() (PMOD0&=~0xC0,LEDCON0 |= 0x02,LEDCON0 &= ~0x01)
#define Set_led0_10ma() (PMOD0&=~0xC0,LEDCON0 |= 0x03)
#define Disable_led1() /*P3.4*/(LEDCON0 &= ~0x0C)
#define Set_led1_2ma() (PMOD0&=~0xC0,LEDCON0 |= 0x04,LEDCON0 &= ~0x08)
#define Set_led1_4ma() (PMOD0&=~0xC0,LEDCON0 |= 0x08,LEDCON0 &= ~0x04)
#define Set_led1_10ma() (PMOD0&=~0xC0,LEDCON0 |= 0x0C)
#define Disable_led2() /*P3.6*/(LEDCON0 &= ~0x30)
#define Set_led2_2ma() (PMOD0&=~0xC0,LEDCON0 |= 0x10,LEDCON0 &= ~0x20)
#define Set_led2_4ma() (PMOD0&=~0xC0,LEDCON0 |= 0x20,LEDCON0 &= ~0x10)
#define Set_led2_10ma() (PMOD0&=~0xC0,LEDCON0 |= 0x30)
#define Disable_led3() /*P3.7*/(LEDCON0 &= ~0xC0)
#define Set_led3_2ma() (PMOD0&=~0xC0,LEDCON0 |= 0x40,LEDCON0 &= ~0x80)
#define Set_led3_4ma() (PMOD0&=~0xC0,LEDCON0 |= 0x80,LEDCON0 &= ~0x40)
#define Set_led3_10ma() (PMOD0&=~0xC0,LEDCON1 |= 0xC0)
#define Disable_led4() /*P4.3*/(LEDCON1 &= ~0x03)
#define Set_led4_2ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x01,LEDCON1 &= ~0x02)
#define Set_led4_4ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x02,LEDCON1 &= ~0x01)
#define Set_led4_10ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x03)
#define Disable_led5() /*P4.4*/(LEDCON1 &= ~0x0C)
#define Set_led5_2ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x04,LEDCON1 &= ~0x08)
#define Set_led5_4ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x08,LEDCON1 &= ~0x04)
#define Set_led5_10ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x0C)
#define Disable_led6() /*P4.5*/(LEDCON1 &= ~0x30)
#define Set_led6_2ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x10,LEDCON1 &= ~0x20)
#define Set_led6_4ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x20,LEDCON1 &= ~0x10)
#define Set_led6_10ma() (PMOD1 &= ~0x03,LEDCON1 |= 0x30)
#define STANDARD_PORT 0
#define LED_PORT_2MA 1
#define LED_PORT_4MA 2
#define LED_PORT_10MA 3
//#define Configure_led(num,type) (LEDCON &= (0xFF & ~(0x03 << (num*2))) , LEDCON |= (type << (num*2)))
#define Led_0_on() (P3_2 = 0)
#define Led_0_off() (P3_2 = 1)
#define Led_0_toggle() (P3_2 = ~P3_2)
#define Led_1_on() (P3_4 = 0)
#define Led_1_off() (P3_4 = 1)
#define Led_1_toggle() (P3_4 = ~P3_4)
#define Led_2_on() (P3_6 = 0)
#define Led_2_off() (P3_6 = 1)
#define Led_2_toggle() (P3_6 = ~P3_6)
#define Led_3_on() (P3_7 = 0)
#define Led_3_off() (P3_7 = 1)
#define Led_3_toggle() (P3_7 = ~P3_7)
#define Led_4_on() (P4_3 = 0)
#define Led_4_off() (P4_3 = 1)
#define Led_4_toggle() (P4_3 = ~P4_3)
#define Led_5_on() (P4_4 = 0)
#define Led_5_off() (P4_4 = 1)
#define Led_5_toggle() (P4_4 = ~P4_4)
#define Led_6_on() (P4_5 = 0)
#define Led_6_off() (P4_5 = 1)
#define Led_6_toggle() (P4_5 = ~P4_5)
/*--------------------------- PORTS ------------------------------------*/
#define Set_p4m_quasi_bidir() (PMOD1 &= ~0x03)
#define Set_p4m_output_pushpull() (PMOD1 &= ~0x02, PMOD1 |= 0x01)
#define Set_p4m_output_lowspeed() (PMOD1 &= ~0x01, PMOD1 |= 0x02)
#define Set_P4m_input_medium_pullup() (PMOD1 |= 0x03)
#define Set_p5h_quasi_bidir() (PMOD1 &= MSK_PMOD1_P5H_QB)
#define Set_p5h_output_pushpull() (PMOD1 &= MSK_PMOD1_P5H_QB, PMOD1 |= MSK_PMOD1_P5H_OPP)
#define Set_p5h_input_weak_pulldown() (PMOD1 &= MSK_PMOD1_P5H_QB, PMOD1 |= MSK_PMOD1_P5H_IWD)
#define Set_P5h_input_weak_pullup() (PMOD1 &= MSK_PMOD1_P5H_QB, PMOD1 |= MSK_PMOD1_P5H_IWU)
#define Set_p5m_quasi_bidir() (PMOD1 &= MSK_PMOD1_P5M_QB)
#define Set_p5m_output_pushpull() (PMOD1 &= MSK_PMOD1_P5M_QB, PMOD1 |= MSK_PMOD1_P5M_OPP)
#define Set_p5m_input_weak_pulldown() (PMOD1 &= MSK_PMOD1_P5M_QB, PMOD1 |= MSK_PMOD1_P5M_IWD)
#define Set_p5m_input_weak_pullUp() (PMOD1 &= MSK_PMOD1_P5M_QB, PMOD1 |= MSK_PMOD1_P5M_IWU)
#define Set_p5l_quasi_bidir() (PMOD1 &= MSK_PMOD1_P5L_QB)
#define Set_p5l_output_pushpull() (PMOD1 &= MSK_PMOD1_P5L_QB, PMOD1 |= MSK_PMOD1_P5L_OPP)
#define Set_p5l_input_medium_pullup() (PMOD1 &= MSK_PMOD1_P5L_QB, PMOD1 |= MSK_PMOD1_P5M_IMU)
#define Set_p5l_input_weak_pullup() (PMOD1 &= MSK_PMOD1_P5L_QB, PMOD1 |= MSK_PMOD1_P5M_IWU)
#define Set_p2_quasi_bidir() (PMOD0 &= MSK_PMOD0_P2_QB)
#define Set_p2_output_pushpull() (PMOD0 &= MSK_PMOD0_P2_QB, PMOD0 |= MSK_PMOD0_P2_OPP)
#define Set_p2_output_lowspeed() (PMOD0 &= MSK_PMOD0_P2_QB, PMOD0 |= MSK_PMOD0_P2_OLS)
#define Set_p2_input_weak_pullup() (PMOD0 &= MSK_PMOD0_P2_QB, PMOD0 |= MSK_PMOD0_P2_IWU)
/*--------------------------- KEYBOARD CONTROLLER ---------------------*/
#define Set_kbd_input_lowlevel_detect()(KBLS = MSK_KBLS_LLD)
#define Reset_kbd_flag0() (KBF &= ~MSK_KBF_RST_FLAG0)
#define Set_kbd_input_stdio() (KBE = MSK_KBE_STDIO)
#define Set_kbd_input_int() (KBE = ~MSK_KBE_STDIO)
/*--------------------------- TIMER CONTROLLERS ---------------------*/
#define Set_timer0_x1_mode() (CKCON |= MSK_T0X2)
#define Set_timer0_x2_mode() (CKCON &=~MSK_T0X2)
#define Set_timer1_x1_mode() (CKCON |= MSK_T1X2)
#define Set_timer1_x2_mode() (CKCON &=~MSK_T1X2)
#define Set_timer2_x1_mode() (CKCON |= MSK_T2X2)
#define Set_timer2_x2_mode() (CKCON &=~MSK_T2X2)
/*__________ O L D D E C L A R A T I O N S __________________________*/
/************************************/
/* DO NOT USE THE FOLLOWING INPUTS */
/************************************/
#define Set_x1_mode_div2() (CKCON0 &= ~0x01, CKRL=0x0F)
#define Set_x1_mode_div4() (CKCON0 &= ~0x01, CKRL=0x0E)
#define Set_x1_mode_div6() (CKCON0 &= ~0x01, CKRL=0x0D)
#define Set_x1_mode_div8() (CKCON0 &= ~0x01, CKRL=0x0C)
#define Set_x1_mode_div12() (CKCON0 &= ~0x01, CKRL=0x0A)
#define Set_x1_mode_div32() (CKCON0 &= ~0x01, CKRL=0x00)
#define Enable_interrupt() (EA = 1)
#define Disable_interrupt() (EA = 0)
#define Led_all_disabled() (LEDCON0 = 0x00, LEDCON1 = 0x00)
#define Select_quartz() (CKSEL &= ~MSK_CKSEL_CKS)
#define Select_Quartz_For_Cpu() (CKSEL &= ~MSK_CKSEL_CKS)
#define Set_PLL_96M() (PLLDIV=VAL_96MHZ)
#define Select_OSC_For_Cpu() (CKSEL &= ~0x01)
#define Select_PLL_For_Cpu() (CKSEL |= 0x01)
#define Select_PLL() (CKSEL |= 0x01)
#define Select_pll() (CKSEL |= 0x01)
#define Enable_PLL() (PLLCON |= MSK_PLLCON_PLLEN)
#define Disable_PLL() (PLLCON &= ~MSK_PLLCON_PLLEN)
#define Lock_PLL() while(PLLCON & MSK_PLLCON_PLOCK)
#define Select_Quartz_For_Scib() (PLLCON |= 0x04)
#define Select_OSC_For_Scib_Usb() (PLLCON |= 0x04)
#define Select_PLL_For_Scib_Usb() (PLLCON &= ~0x04)
#define Select_pll_For_Cpu() (CKSEL |= 0x01)
#define Set_p4m_quasi_bidir() (PMOD1 &= ~0x03)
#define Set_p4m_output_push_pull() (PMOD1 &= ~0x02); (PMOD1 |= 0x01)
#define Set_p4m_output_low_speed() (PMOD1 &= ~0x01); (PMOD1 |= 0x02)
#define Set_P4m_input_medium_pull_up() (PMOD1 |= 0x03)
#define Set_p5h_output_push_pull() (PMOD1 &= MSK_PMOD1_P5H_QB); (PMOD1 |= MSK_PMOD1_P5H_OPP)
#define Set_p5h_input_weak_pull_down() (PMOD1 &= MSK_PMOD1_P5H_QB); (PMOD1 |= MSK_PMOD1_P5H_IWD)
#define Set_P5h_input_weak_pull_up() (PMOD1 &= MSK_PMOD1_P5H_QB); (PMOD1 |= MSK_PMOD1_P5H_IWU)
#define Set_p5m_output_push_pull() (PMOD1 &= MSK_PMOD1_P5M_QB); (PMOD1 |= MSK_PMOD1_P5M_OPP)
#define Set_p5m_input_weak_pull_down() (PMOD1 &= MSK_PMOD1_P5M_QB); (PMOD1 |= MSK_PMOD1_P5M_IWD)
#define Set_p5m_input_weak_pull_Up() (PMOD1 &= MSK_PMOD1_P5M_QB); (PMOD1 |= MSK_PMOD1_P5M_IWU)
#define Set_p5l_output_push_pull() (PMOD1 &= MSK_PMOD1_P5L_QB); (PMOD1 |= MSK_PMOD1_P5L_OPP)
#define Set_p5l_input_medium_pull_up() (PMOD1 &= MSK_PMOD1_P5L_QB); (PMOD1 |= MSK_PMOD1_P5M_IMU)
#define Set_p5l_input_weak_pull_up() (PMOD1 &= MSK_PMOD1_P5L_QB); (PMOD1 |= MSK_PMOD1_P5M_IWU)
#define Set_p2_output_push_pull() (PMOD0 &= MSK_PMOD0_P2_QB); (PMOD0 |= MSK_PMOD0_P2_OPP)
#define Set_p2_output_low_peed() (PMOD0 &= MSK_PMOD0_P2_QB); (PMOD0 |= MSK_PMOD0_P2_OLS)
#define Set_p2_input_weak_pull_up() (PMOD0 &= MSK_PMOD0_P2_QB); (PMOD0 |= MSK_PMOD0_P2_IWU)
#define PLL_3MHz 0xF0
#define PLL_4MHz 0xC0
#define PLL_6MHz 0x70
#define PLL_8MHz 0xB0
#define PLL_12MHz 0x30
#define PLL_16MHz 0x20
#define PLL_18MHz 0x72
#define PLL_20MHz 0xB4
#define PLL_24MHz 0x10
#define PLL_32MHz 0x21
#define PLL_40MHz 0xB9
#define Set_cpu_on_pll(CPU_FREQ) \
switch ( CPU_FREQ ) \
{ \
case (24): \
Set_cpu_24mhz_pll(); \
break; \
case (16): \
Set_cpu_16mhz_pll(); \
break; \
case (12): \
Set_cpu_12mhz_pll(); \
break; \
case (8): \
Set_cpu_8mhz_pll(); \
break; \
}
#define Config_clock_cpu(CPU_MODE, CPU_FREQ) \
{ \
if (CPU_MODE == CPU_PLL) {Set_cpu_pll(16-48/CPU_FREQ);} \
else \
{ \
if (CPU_FREQ ==8) {Set_cpu_8mhz_osc();} \
else {Set_cpu_osc(16-4/CPU_FREQ);} \
} \
}
#endif /* _MCU_DRV_H_ */
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