?? boot5402.asm
字號:
STM #0000h,SPSD0 ; DISABLES TRANSMIT.
STM RCR1_SUBADDR,SPSA0 ; Set the receive word length to 16-bit.
STM #0040H,SPSD0
STM RCR2_SUBADDR,SPSA0 ; Set the receive word length to 16-bit.
STM #0041H,SPSD0 ; Single Phase, 16-bit, No Compan,1bit Delay.
STM SRGR1_SUBADDR,SPSA0
STM #0000H,SPSD0 ; Clear the clkdiv and frame width.
STM SRGR2_SUBADDR,SPSA0
STM #0000H,SPSD0 ; Clksm=0 External source.
STM PCR_SUBADDR,SPSA0
STM #0000H,SPSD0 ; BCLKX and FSX configured as inputs
STM SPCR1_SUBADDR,SPSA0
STM #0001H,SPSD0 ; ENABLES RECEIVE.
********************************************************************************
* 2. BSP1 is configured for 8-bit, clk input, fm input. *
********************************************************************************
STM SPCR1_SUBADDR,SPSA1
STM #0000h,SPSD1 ; DISABLES RECEIVE.
STM SPCR2_SUBADDR,SPSA1
STM #0000h,SPSD1 ; DISABLES TRANSMIT.
STM RCR1_SUBADDR,SPSA1 ; Set the receive word length to 8-bit.
STM #0000H,SPSD1
STM RCR2_SUBADDR,SPSA1 ; Set the receive word length to 8-bit.
STM #0001H,SPSD1 ; Single Phase, 8-bit, No Compan,1bit Delay
STM SRGR1_SUBADDR,SPSA1
STM #0000H,SPSD1 ; Clear the clkdiv and frame width.
STM SRGR2_SUBADDR,SPSA1
STM #0000H,SPSD1 ; Clksm=0 External source.
STM PCR_SUBADDR,SPSA1
STM #0000H,SPSD1 ; BCLKX and FSX configured as inputs
STM SPCR1_SUBADDR,SPSA1
STM #0001H,SPSD1 ; ENABLES RECEIVE.
********************************************************************************
***
rsbx xf ; signal ready-to-receive
chk_ser bitf ifr, #400h ; check RINT1 flag
cc BSP1, tc ;
bitf ifr, #10h ; check RINT0 flag
cc BSP0, tc ;
bc pasyini, bio ; check for I/O boot
**************RDP***************
* Add HPI entry check here. *
********************************
ldm HPIentry, a ; Get HPI entry vector.
bc hpiboot, aneq ; If not zero, HPI boot.
b chk_ser ; else, keep looping.
********************************
*****************************************************************
* End-boot, simply branch to source address
*****************************************************************
endboot
ldu @entry,a ; branch to the entry point
add @xentry,16,a ;
hpiboot fbacc a
*****************************************************************
* Bootload from 8-bit memory, MS byte first
*****************************************************************
par08
ld *ar1+, 8, a ; read MSB of SWWSR value
mvdk *ar1+, ar3 ; read LSB of SWWSR value
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stlm a,swwsr ; store A to SWWSR
ld *ar1+, 8, a ; read MSB of BSCR value
mvdk *ar1+, ar3 ; read LSB of BSCR value
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stlm a,bscr ; store A to BSCR
ld *ar1+, 8, a ; read MSB of XPC of entry addr
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stl a,@xentry ; stor A to xentry
ld *ar1+, 8, a ; read MSB of entry address
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stl a,@entry ; stor A to entry
par08_1 ld *ar1+, 8, a ; get MSB of block size (16-bit words)
and #0ff00h, a ; Clear grd bits, and upper word. Rev1.01
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
bcd endboot,aeq ; section size =0 indicate boot end
sub #1,a,b ; brc = section size - 1
stlm b, brc ; update block repeat counter register
ld *ar1+, 8, a ; get MSB of XPC of destination
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
stl a,@dest ; @dest <-- XPC
ld *ar1+, 8, a ; get MSB of destinationaddress
************* Bug fix ******************************************************
and #0ff00h,a ;force AG, AH to zero for correct calculation
;of the 23-bit destination address.
;(11/10/99 PMJ2) 1.03
****************************************************************************
mvdk *ar1+, ar3 ; read LSB
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, a ; Concatenate
add @dest,16,a ; acc A <-- 23-bit destination address
rptb xfr08-1
ld *ar1+, 8, b ; read MSB of data
mvdk *ar1+, ar3 ; read LSB of data
andm #0ffh, @ar3 ; Mask off upper 8-bits
or @ar3, b ; Concatenate
rpt #10 ;insert at least 10 cycles
nop ; between read and write
writa BL ; write object data to destination
add #1, a ; increment destination address
xfr08
b par08_1
*****************************************************************
* Bootload from 16-bit memory
*****************************************************************
par16
ld *ar1+, a ; read desired value of SWWSR
stlm a, @swwsr ; store in SWWSR
ld *ar1+, a ; read desired value of BSCR
and #0FFFEh,a ; ensure EXIO bit is off
stlm a, @bscr ; store in BSCR
ld *ar1+, a ; read XPC of entry point address
stl a, @xentry ; and store
ld *ar1+, a ; read low 16-bits of entry point addr
stl a, @entry ; and store
par16_1 ld *ar1+,a ; load the size of section to A
bcd endboot,aeq ; section size =0 indicate boot end
sub #1,a,b ; brc = section size - 1
stlm b, brc ; update BRC
ld *ar1+,a ; get the XPC of destination (A22-A16)
stl a,@dest ; store XPC at data memory @dest
ldu *ar1+,a ; get address of destination in A(15-0)
stlm a,ar2 ; store dest address at ar2
add @dest,16,a ; acc A <--- 23-bit destination address
rptb xfr16-1
mvdk *ar1+, ar3 ; read object data
rpt #10 ;insert at least 10 cycles
nop ; between read and write
writa @ar3 ; write object data to destination
add #1,a ;increment desintation address
xfr16
b par16_1
*****************************************************************
* Bootload from BSP serial port
*****************************************************************
ser_in
rsbx tc ; clear flag
bcd $, ntc ; begin receive data routine
BITF *AR6,#0002h ; Bit test on RRDY. Reception of a new word.
RET
BSP0
STM SPCR1_SUBADDR,SPSA0 ; Set up to read the value of the
STM SPSD0,AR6 ; SPCR10 reg, RRDY.
stm #drr10,ar1 ; ar1 <-- drr0
stm #010h, @ifr ; clear BRINT0 flag
b SP_in_16 ; check BSP
BSP1
STM SPCR1_SUBADDR,SPSA1 ; Set up to read the value of the
STM SPSD1,AR6 ; SPCR10 reg, RRDY.
stm #drr11,ar1 ; ar1 <-- drr0
stm #400h, @ifr ; clear BRINT1 flag
b SP_in_8 ; check BSP
*****************************************************************
* McBSP Bootload in 16-bit mode *
*****************************************************************
SP_in_16
ldm *ar1, a ; acc A <-- DRR
sub #10AAh, a, b ; acc A = 0x10AA ?
bc ser_in_16, beq ; 16-bit serial mode
ret
ser_in_16
;The dummy words are read to maintain
; hex converter compatibility with
; the 548/549
call ser_in ; call SP input sub
mvdk *ar1, temp0 ; temp0 <-- drr0 (DUMMY WORD)
call ser_in ; call SP input sub
mvdk *ar1, temp1 ; temp1 <-- drr0 (DUMMY WORD)
call ser_in ; call SP input sub
mvdk *ar1, temp2 ; temp2 <-- drr0 (DUMMY WORD)
call ser_in ; call SP input sub
mvdk *ar1, temp3 ; temp3 <-- drr0 (DUMMY WORD)
call ser_in ; call SP input sub
mvdk *ar1, xentry ; xentry <-- drr0 (XPC of entry point)
call ser_in ; call SP input sub
mvdk *ar1, entry ; temp0 <-- drr0 (entry point)
SP16_in_1
call ser_in ; call SP input sub
ldu *ar1, a ; acc A <-- drr0 (section size)
bcd endboot,aeq ; section size =0 indicate boot end
sub #1,a,b ; brc = section size - 1
stlm b, brc ; update block repeat counter register
call ser_in ; call SP input sub
mvdk *ar1, dest ; xentry <-- drr0 (XPC of dest)
call ser_in ; call SP input sub
ldu *ar1, a ; acc A <-- destination addr
add @dest, 16, a ;
rptb sfxr16_in-1
call ser_in ; call SP input sub
ldu *ar1, b ; acc B <-- drr0 (input dada)
writa @BL ; [acc A] <-- acc BL
add #1, a ; increment dest add
sfxr16_in
b SP16_in_1 ; check next section
*****************************************************************
* 8-bit mode input clk,frm *
*****************************************************************
DBsreadA
call ser_in ; call SP input sub
ld *ar1, 8, a ; acc A <-- junkbyte.high byte
and #0ff00h, a ; acc A <-- high.byte
stl a, @hbyte ; save high byte
call ser_in ; call SP input sub
ldu *ar1, a ; acc A <-- junkbyte.low byte
and #0ffh, a ; acc A <-- low byte
or @hbyte, a ; acc A <-- high byte.low byte
ret
SP_in_8
ldm *ar1, a ; acc A <-- DRR
sub #0008h, a ; acc A = 0008
rc aneq
call ser_in ; call SP input sub
ldm *ar1, a ; acc A <-- DRR
sub #0AAh, a ; acc A = 00aa
rc aneq
ser_08
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