//*********************************************************
//
//  pci_dma_test.c : Program to test TPCI_LIB functions for
//  block DMAs over PCI on the TigerSharc platform.
//
//  PROVIDED BY:
//  ------------
//  BittWare, Inc.
//  33 North Main Street
//  Concord, NH  03301
//  Ph: 603-226-0404
//  Fax: 603-226-6667
//  WWW: www.bittware.com
//  E-mail: support@bittware.com
//
//  Copyright (c) 2002
//
//  The user is hereby granted a non-exclusive license to use and or 
//  modify this software provided that it runs on BittWare hardware.  
//  Usage of this software on non-BittWare hardware without the express 
//  written permission of BittWare is strictly prohibited.
//    Ver.  Dates     Author  Changes                                
//    ----  --------  ------  -----------------------------
//    1.0   04/03/02   rpc     Create
//
//*********************************************************
#include <sysreg.h>
#include "tfin.h"
#include "tfin_pci.h"
#include "utils.h"

#define BUF_SIZE   4096

// hardcode the buffer address here if you so choose
//volatile int pci_addr = 0x00432000;
volatile int pci_addr = 0x0;
volatile int done;
unsigned int addr;
int read_ticks, write_ticks;
float read_rate, write_rate, average_read_rate, average_write_rate;

int tx_stat;
int rx_stat;
int xfer_errors[16] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
                       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
int errors = 0;
int loop;
int loops_to_run = 0x1000;
int src_array[BUF_SIZE];
int dst_array[BUF_SIZE];
volatile int rx_intr_count = 0;

void fin_rx_dma_complete(int sig)
{
    //Fin_PCI_CB_DMA_Clear_Interrupt();
	rx_intr_count++;
}

////////////////////////////////////////////////////////////////////////////////
//               main
////////////////////////////////////////////////////////////////////////////////
void main(void)
{
    int i,j; 

	// Set up Tiger
	init_Tiger();
	done = 0;

	prep_leds();

	// Flag 2 is a done indicator and flag 3 toggles for each completed DMA
	// also, at done Flag 3 is illuminated if there were no errors
	leds_off(FLG2 | FLG3);

	/* Init the source buffer with some static data patterns, breaking it into 16 pieces 
	   and leaving the upper half for counters in each test							*/

	// Alternating bits both within and between bytes
	for (i=0; i<(BUF_SIZE/16); i++)
	{
		src_array[i] = 0xaa55aa55;			
	}

	// Reverse alternating bits
	for (i=(BUF_SIZE/16); i<(2*(BUF_SIZE/16)); i++)
	{
		src_array[i] = 0x55aa55aa;
	}

	// All bits on and off between nibbles
	for (i=(2*(BUF_SIZE/16)); i<(3*(BUF_SIZE/16)); i++)
	{
		src_array[i] = 0x0f0f0f0f;		
	}

	// Reverse all bits on and off betwen nibbles
	for (i=(3*(BUF_SIZE/16)); i<(4*(BUF_SIZE/16)); i++)
	{
		src_array[i] = 0xf0f0f0f0;
	}

	// All bits on and off between bytes
	for (i=(4*(BUF_SIZE/16)); i<(5*(BUF_SIZE/16)); i++)
	{
		src_array[i] = 0x00ff00ff;		
	}

	// Reverse all bits on and off
	for (i=(5*(BUF_SIZE/16)); i<(6*(BUF_SIZE/16)); i++)
	{
		src_array[i] = 0xff00ff00;
	}

	// All bits on and off on link word size (128 bit) boundaries
	for (i=(6*(BUF_SIZE/16)); i<(7*(BUF_SIZE/16)); i+=8)
	{
		for (j=0; j<4; j++)
			src_array[i+j] = 0x0;
		for (j=4; j<8; j++)
			src_array[i+j] = 0xffffffff;
	}

	// All bits on and off on 32 bit link word size boundaries
	for (i=(7*(BUF_SIZE/16)); i<(8*(BUF_SIZE/16)); i+=2)
	{
		src_array[i] = 0x0;
		src_array[i+1] = 0xffffffff;
	}


	// Init the PCI interface
	TigerFin_PCI_Init();

	// If the host hasn't set a pci address, use my own internal memory, which means
	// it goes out the SharcFIN onto the local PCI bus and back in again
	if (pci_addr == 0x0) {
		TigerFin_PCI_CFG_Read(HOST_BAR4_ADDR, (int *)&pci_addr);
		// offset into my internal memory 2 block
		pci_addr &= 0xFFFFFFF0;
		pci_addr += (GetIDC() * 0x200000 + 0x100008) * 4;
		SetFIN(THRESH_PREF_CNTL, 0x1000);            // setup prefetching to move data quickly
	}

	average_read_rate = 0;
	average_write_rate = 0;

	for(loop = 0; loop < loops_to_run; loop++)
	{

		// Fill the rest of the source buffer
		// Put incrementing pattern in half
		for (i=(2*(BUF_SIZE/4));i<(3*(BUF_SIZE/4));i++)
	    {
	        src_array[i] = i + (loop << 16);
	    }
	
		// Put inverse of incrementing pattern in other half
		for (i=(3*(BUF_SIZE/4));i<(4*(BUF_SIZE/4));i++)
	    {
	        src_array[i] = ~(i + (loop << 16));
	    }

		// Time the block transfers and use it to compute average read and write rates

		init_timer(0, 0x0, 0xFFFFFFFF);
		start_timer(0);

		tx_stat = TigerFin_PCI_CB_DMA_Write(src_array, (int *)pci_addr, BUF_SIZE, 1, 0, 0, 1);

		write_ticks = 0xFFFFFFFF - stop_timer(0);

		toggle_leds(FLG3);

		init_timer(0, 0x0, 0xFFFFFFFF);
		start_timer(0);

		rx_stat = TigerFin_PCI_CB_DMA_Read(dst_array, (int *)pci_addr, BUF_SIZE, 1, 0, 0 ,1, 0);

		read_ticks = 0xFFFFFFFF - stop_timer(0);

		toggle_leds(FLG3);
		for(i = 0; i < BUF_SIZE; i++)
		{
		    if(dst_array[i] != src_array[i])
			    errors++;
		}
		// rate = #ofbytes/time 
		// #ofbytes = 4 * #of32bitwords
		// time = ticks*timerpertick
		// timerpertick = 1/250MHz

		read_rate = (4 * BUF_SIZE * 250000000.0) / (float)read_ticks; 
		write_rate = (4 * BUF_SIZE * 250000000.0) / (float)write_ticks; 
		average_read_rate += read_rate;
		average_write_rate += write_rate;
	}

	average_read_rate /= (float)loops_to_run;
	average_write_rate /= (float)loops_to_run;

	/*
	// FlyBy function test.
	init_timer(0, 0x0, 0xFFFFFFFF);
	start_timer(0);

	rx_stat = TigerFin_PCI2SDRAM_Flyby_Read((int *)SDRAM_ADDR, (int *)pci_addr, BUF_SIZE, 1, 0, 1);

	read_ticks = 0xFFFFFFFF - stop_timer(0);

	toggle_flags(FLG3);

	init_timer(0, 0x0, 0xFFFFFFFF);
	start_timer(0);

	tx_stat = TigerFin_SDRAM2PCI_Flyby_Write((int *)SDRAM_ADDR, (int *)(pci_addr + (4*BUF_SIZE)), BUF_SIZE, 1, 0);

	write_ticks = 0xFFFFFFFF - stop_timer(0);

	read_rate = (4 * BUF_SIZE * 250000000.0) / (float)read_ticks; 
	write_rate = (float)(4 * BUF_SIZE * 250000000.0) / (float)write_ticks; 
	*/

	leds_on(FLG2);
	if (errors) leds_off(FLG3);
    else leds_on(FLG3);
	// do not allow the code to end due to compiler probs/TS anomallies
	while (1) done = 1;
}