/***********************************************************************/
/*  13506 HAL INF       (do not remove)                                 */
/*  HAL_STRUCT Information generated by 13506CFG.EXE                    */
/*                                                                     */
/*  Copyright (c) 1997, 2001 Epson Research and Development, Inc.      */
/*  All Rights Reserved.                                               */
/*                                                                     */
/*  Include this file ONCE in your primary source file                 */
/***********************************************************************/


HAL_STRUCT HalInfo =
{
  "1356 HAL EXE",          /* ID string */
  0x1234,                  /* Detect Endian */
  sizeof(HalInfo),         /* Size */
  fVALID_LCD | fVALID_CRT,   /* Flags */

  {  
     /* Basic Registers */
     {REG_MISC, 0x00},   /* enable host interface */

     /* First disable all output devices */
     {REG_DISPLAY_MODE, 0x00},

     /* General I/O Pins Registers */
     {REG_GPIO_CONFIG, 0x00},
     {REG_GPIO_CTRL, 0x00},

     /* Clock Configuration Registers */
     {REG_MEM_CLOCK_CFG, 0x01},
     {REG_LCD_PCLK_CFG, 0x00},
     {REG_CRTTV_PCLK_CFG, 0x02},
     {REG_MPCLK_CFG, 0x03},
     {REG_CPU2MEM_WAIT_SEL, 0x00},

     /* Memory Configuration Registers */
     {REG_MEM_CFG, 0x00},
     {REG_DRAM_REFRESH, 0x06},
     {REG_DRAM_TIMINGS_CTRL0, 0x12},
     {REG_DRAM_TIMINGS_CTRL1, 0x02},

     /* Panel Configuration Registers */
     {REG_PANEL_TYPE, 0x25},
     {REG_MOD_RATE, 0x00},
     {REG_LCD_HDP, 0x4f},
     {REG_LCD_HNDP, 0x13},
     {REG_TFT_FPLINE_START, 0x01},
     {REG_TFT_FPLINE_PULSE, 0x0b},
     {REG_LCD_VDP0, 0xdf},
     {REG_LCD_VDP1, 0x01},
     {REG_LCD_VNDP, 0x2c},
     {REG_TFT_FPFRAME_START, 0x0b},
     {REG_TFT_FPFRAME_PULSE, 0x01},

     /* LCD Display Mode Registers */
     {REG_LCD_DISPLAY_MODE, 0x03},
     {REG_LCD_MISC, 0x00},
     {REG_LCD_START_ADDR0, 0x00},
     {REG_LCD_START_ADDR1, 0x00},
     {REG_LCD_START_ADDR2, 0x00},
     {REG_LCD_MEM_ADDR_OFFSET0, 0x40},
     {REG_LCD_MEM_ADDR_OFFSET1, 0x01},
     {REG_LCD_PIXEL_PANNING, 0x00},
     {REG_LCD_FIFO_HIGH_THRESHOLD, 0x00},
     {REG_LCD_FIFO_LOW_THRESHOLD, 0x00},

     /* CRT/TV Configuration Registers */
     {REG_CRTTV_HDP, 0x4f},
     {REG_CRTTV_HNDP, 0x13},
     {REG_CRTTV_HRTC_START, 0x01},
     {REG_CRT_HRTC_PULSE, 0x0b},
     {REG_CRTTV_VDP0, 0xdf},
     {REG_CRTTV_VDP1, 0x01},
     {REG_CRTTV_VNDP, 0x2b},
     {REG_CRTTV_VRTC_START, 0x09},
     {REG_CRT_VRTC_PULSE, 0x01},
     {REG_TV_OUTPUT_CTRL, 0x10},

     /* CRT/TV Display Mode Registers */
     {REG_CRTTV_DISPLAY_MODE, 0x03},
     {REG_CRTTV_START_ADDR0, 0x00},
     {REG_CRTTV_START_ADDR1, 0x00},
     {REG_CRTTV_START_ADDR2, 0x00},
     {REG_CRTTV_MEM_ADDR_OFFSET0, 0x40},
     {REG_CRTTV_MEM_ADDR_OFFSET1, 0x01},
     {REG_CRTTV_PIXEL_PANNING, 0x00},
     {REG_CRTTV_FIFO_HIGH_THRESHOLD, 0x00},
     {REG_CRTTV_FIFO_LOW_THRESHOLD, 0x00},

     /* LCD Ink/Cursor Registers */
     {REG_LCD_INK_CURS_CTRL, 0x00},
     {REG_LCD_INK_CURS_START_ADDR, 0x00},
     {REG_LCD_CURSOR_X_POS0, 0x00},
     {REG_LCD_CURSOR_X_POS1, 0x00},
     {REG_LCD_CURSOR_Y_POS0, 0x00},
     {REG_LCD_CURSOR_Y_POS1, 0x00},
     {REG_LCD_INK_CURS_BLUE0, 0x00},
     {REG_LCD_INK_CURS_GREEN0, 0x00},
     {REG_LCD_INK_CURS_RED0, 0x00},
     {REG_LCD_INK_CURS_BLUE1, 0x00},
     {REG_LCD_INK_CURS_GREEN1, 0x00},
     {REG_LCD_INK_CURS_RED1, 0x00},
     {REG_LCD_INK_CURS_FIFO, 0x00},

     /* CRT/TV Ink/Cursor Registers */
     {REG_CRTTV_INK_CURS_CTRL, 0x00},
     {REG_CRTTV_INK_CURS_START_ADDR, 0x00},
     {REG_CRTTV_CURSOR_X_POS0, 0x00},
     {REG_CRTTV_CURSOR_X_POS1, 0x00},
     {REG_CRTTV_CURSOR_Y_POS0, 0x00},
     {REG_CRTTV_CURSOR_Y_POS1, 0x00},
     {REG_CRTTV_INK_CURS_BLUE0, 0x00},
     {REG_CRTTV_INK_CURS_GREEN0, 0x00},
     {REG_CRTTV_INK_CURS_RED0, 0x00},
     {REG_CRTTV_INK_CURS_BLUE1, 0x00},
     {REG_CRTTV_INK_CURS_GREEN1, 0x00},
     {REG_CRTTV_INK_CURS_RED1, 0x00},
     {REG_CRTTV_INK_CURS_FIFO, 0x00},

     /* BitBlt Configuration Registers */
     {REG_BITBLT_CTRL0, 0x00},
     {REG_BITBLT_CTRL1, 0x00},
     {REG_BITBLT_ROP_CODE, 0x00},
     {REG_BITBLT_OPERATION, 0x00},
     {REG_BITBLT_SRC_START_ADDR0, 0x00},
     {REG_BITBLT_SRC_START_ADDR1, 0x00},
     {REG_BITBLT_SRC_START_ADDR2, 0x00},
     {REG_BITBLT_DEST_START_ADDR0, 0x00},
     {REG_BITBLT_DEST_START_ADDR1, 0x00},
     {REG_BITBLT_DEST_START_ADDR2, 0x00},
     {REG_BITBLT_MEM_ADDR_OFFSET0, 0x00},
     {REG_BITBLT_MEM_ADDR_OFFSET1, 0x00},
     {REG_BITBLT_WIDTH0, 0x00},
     {REG_BITBLT_WIDTH1, 0x00},
     {REG_BITBLT_HEIGHT0, 0x00},
     {REG_BITBLT_HEIGHT1, 0x00},
     {REG_BITBLT_BACKGND_COLOR0, 0x00},
     {REG_BITBLT_BACKGND_COLOR1, 0x00},
     {REG_BITBLT_FOREGND_COLOR0, 0x00},
     {REG_BITBLT_FOREGND_COLOR1, 0x00},

     /* Look-Up Table Registers */
     {REG_LUT_MODE, 0x00},
     {REG_LUT_ADDR, 0x00},
     {REG_LUT_DATA, 0x00},

     /* Power Save Configuration Registers */
     {REG_PWR_SAVE_CFG, 0x00},
     {REG_PWR_SAVE_STATUS, 0x00},

     /* Miscellaneous Registers */
     {REG_CPU2MEM_WATCHDOG, 0x00},

     /* Common Display Mode Register */
     {REG_DISPLAY_MODE, 0x02},

     {FINISHED_REG_CFG, 0}
  },

  25175,           /* ClkI (kHz)      */
  25175,           /* ClkI2 (kHz)     */
#ifdef INTEL_DOS
    8000,              /* Bus Clock (kHz) */
#elif defined(MPC8xx)
    20000,             /* Bus Clock (kHz) */
#else
    40000,             /* Bus Clock (kHz) */
#endif

#ifdef INTEL_DOS
    0x00e00000,        /* Physical Address of Registers      */
    0x00c00000,        /* Physical Address of Display Memory */
#elif defined(BCC68K)
    0x00100000,        /* Physical Address of Registers      */
    0x00200000,        /* Physical Address of Display Memory */
#elif defined(IDP68K)
    0x00F80000,        /* Physical Address of Registers      */
    0x00F00000,        /* Physical Address of Display Memory */
#elif defined(LCEVBSH3)
    0x14000000,        /* Physical Address of Registers      */
    0x04000000,        /* Physical Address of Display Memory */
#elif defined(MPC8xx)
    0x00400000,        /* Physical Address of Registers      */
    0x00600000,        /* Physical Address of Display Memory */
#else
    0x00000000,        /* Physical Address of Registers      */
    0x00000000,        /* Physical Address of Display Memory */
#endif

  60,              /* Panel Frame Rate (Hz)              */
  60,              /* CRT Frame Rate (Hz)                */
  50,              /* Memory speed (ns)                  */
  32000,           /* DRAM Refresh Time (us)             */
  84,              /* Trc: Ras to Cas Delay (ns)         */
  30,              /* Trp: Ras Precharge time (ns)       */
  50,              /* Tras: Ras Pulse Width time in ns   */
  50,              /* Trac: Ras Access Charge time (ns)  */
  TRUE             /* Enable TV flicker filter           */
};