?? appcfg.h
字號:
/******************************************************************************/
/* */
/* HAL_STRUCT Information generated by 13506CFG.EXE */
/* */
/* Copyright (c) 1998, 2001 Epson Research and Development, Inc. */
/* All rights reserved. */
/* */
/* Panel: (inactive) 640x480 60Hz TFT Single 18-bit (PCLK=25175kHz) */
/* CRT: (active) 640x480 60Hz (PCLK=25175kHz) */
/* Memory: 50ns EDO-DRAM with 2-CAS#: 8ms refresh (MCLK=40000kHz) */
/* */
/* Include this file ONCE in your primary source file. */
/* Set compiler options to pack the structure on a byte boundary. */
/* */
/******************************************************************************/
HAL_STRUCT HalInfo =
{
"1356 HAL EXE", /* ID string */
0x1234, /* Detect Endian */
sizeof(HAL_STRUCT), /* Size */
0 | fVALID_LCD | fVALID_CRT , /* Flags */
{
/* Registers */
{REG_MISC ,0x00}, /* Reg 1h */
{REG_DISPLAY_MODE ,0x00}, /* Reg 1fch */
{REG_GPIO_CONFIG ,0x00}, /* Reg 4h */
{REG_GPIO_CTRL ,0x00}, /* Reg 8h */
{REG_MEM_CLOCK_CFG ,0x01}, /* Reg 10h */
{REG_LCD_PCLK_CFG ,0x00}, /* Reg 14h */
{REG_CRTTV_PCLK_CFG ,0x00}, /* Reg 18h */
{REG_MPCLK_CFG ,0x02}, /* Reg 1ch */
{REG_CPU2MEM_WAIT_SEL ,0x01}, /* Reg 1eh */
{REG_MEM_CFG ,0x00}, /* Reg 20h */
{REG_DRAM_REFRESH ,0x04}, /* Reg 21h */
{REG_DRAM_TIMINGS_CTRL0 ,0x01}, /* Reg 2ah */
{REG_DRAM_TIMINGS_CTRL1 ,0x01}, /* Reg 2bh */
{REG_PANEL_TYPE ,0x25}, /* Reg 30h */
{REG_MOD_RATE ,0x00}, /* Reg 31h */
{REG_LCD_HDP ,0x4f}, /* Reg 32h */
{REG_LCD_HNDP ,0x13}, /* Reg 34h */
{REG_TFT_FPLINE_START ,0x01}, /* Reg 35h */
{REG_TFT_FPLINE_PULSE ,0x0b}, /* Reg 36h */
{REG_LCD_VDP0 ,0xdf}, /* Reg 38h */
{REG_LCD_VDP1 ,0x01}, /* Reg 39h */
{REG_LCD_VNDP ,0x2c}, /* Reg 3ah */
{REG_TFT_FPFRAME_START ,0x0b}, /* Reg 3bh */
{REG_TFT_FPFRAME_PULSE ,0x01}, /* Reg 3ch */
{REG_LCD_DISPLAY_MODE ,0x03}, /* Reg 40h */
{REG_LCD_MISC ,0x00}, /* Reg 41h */
{REG_LCD_START_ADDR0 ,0x00}, /* Reg 42h */
{REG_LCD_START_ADDR1 ,0x00}, /* Reg 43h */
{REG_LCD_START_ADDR2 ,0x00}, /* Reg 44h */
{REG_LCD_MEM_ADDR_OFFSET0 ,0x40}, /* Reg 46h */
{REG_LCD_MEM_ADDR_OFFSET1 ,0x01}, /* Reg 47h */
{REG_LCD_PIXEL_PANNING ,0x00}, /* Reg 48h */
{REG_LCD_FIFO_HIGH_THRESHOLD ,0x00}, /* Reg 4ah */
{REG_LCD_FIFO_LOW_THRESHOLD ,0x00}, /* Reg 4bh */
{REG_CRTTV_HDP ,0x4f}, /* Reg 50h */
{REG_CRTTV_HNDP ,0x13}, /* Reg 52h */
{REG_CRTTV_HRTC_START ,0x01}, /* Reg 53h */
{REG_CRT_HRTC_PULSE ,0x0b}, /* Reg 54h */
{REG_CRTTV_VDP0 ,0xdf}, /* Reg 56h */
{REG_CRTTV_VDP1 ,0x01}, /* Reg 57h */
{REG_CRTTV_VNDP ,0x2b}, /* Reg 58h */
{REG_CRTTV_VRTC_START ,0x09}, /* Reg 59h */
{REG_CRT_VRTC_PULSE ,0x01}, /* Reg 5ah */
{REG_TV_OUTPUT_CTRL ,0x10}, /* Reg 5bh */
{REG_CRTTV_DISPLAY_MODE ,0x05}, /* Reg 60h */
{REG_CRTTV_START_ADDR0 ,0x00}, /* Reg 62h */
{REG_CRTTV_START_ADDR1 ,0x00}, /* Reg 63h */
{REG_CRTTV_START_ADDR2 ,0x00}, /* Reg 64h */
{REG_CRTTV_MEM_ADDR_OFFSET0 ,0x40}, /* Reg 66h */
{REG_CRTTV_MEM_ADDR_OFFSET1 ,0x01}, /* Reg 67h */
{REG_CRTTV_PIXEL_PANNING ,0x00}, /* Reg 68h */
{REG_CRTTV_FIFO_HIGH_THRESHOLD ,0x00}, /* Reg 6ah */
{REG_CRTTV_FIFO_LOW_THRESHOLD ,0x00}, /* Reg 6bh */
{REG_LCD_INK_CURS_CTRL ,0x00}, /* Reg 70h */
{REG_LCD_INK_CURS_START_ADDR ,0x01}, /* Reg 71h */
{REG_LCD_CURSOR_X_POS0 ,0x00}, /* Reg 72h */
{REG_LCD_CURSOR_X_POS1 ,0x00}, /* Reg 73h */
{REG_LCD_CURSOR_Y_POS0 ,0x00}, /* Reg 74h */
{REG_LCD_CURSOR_Y_POS1 ,0x00}, /* Reg 75h */
{REG_LCD_INK_CURS_BLUE0 ,0x00}, /* Reg 76h */
{REG_LCD_INK_CURS_GREEN0 ,0x00}, /* Reg 77h */
{REG_LCD_INK_CURS_RED0 ,0x00}, /* Reg 78h */
{REG_LCD_INK_CURS_BLUE1 ,0x1f}, /* Reg 7ah */
{REG_LCD_INK_CURS_GREEN1 ,0x3f}, /* Reg 7bh */
{REG_LCD_INK_CURS_RED1 ,0x1f}, /* Reg 7ch */
{REG_LCD_INK_CURS_FIFO ,0x00}, /* Reg 7eh */
{REG_CRTTV_INK_CURS_CTRL ,0x00}, /* Reg 80h */
{REG_CRTTV_INK_CURS_START_ADDR ,0x01}, /* Reg 81h */
{REG_CRTTV_CURSOR_X_POS0 ,0x00}, /* Reg 82h */
{REG_CRTTV_CURSOR_X_POS1 ,0x00}, /* Reg 83h */
{REG_CRTTV_CURSOR_Y_POS0 ,0x00}, /* Reg 84h */
{REG_CRTTV_CURSOR_Y_POS1 ,0x00}, /* Reg 85h */
{REG_CRTTV_INK_CURS_BLUE0 ,0x00}, /* Reg 86h */
{REG_CRTTV_INK_CURS_GREEN0 ,0x00}, /* Reg 87h */
{REG_CRTTV_INK_CURS_RED0 ,0x00}, /* Reg 88h */
{REG_CRTTV_INK_CURS_BLUE1 ,0x1f}, /* Reg 8ah */
{REG_CRTTV_INK_CURS_GREEN1 ,0x3f}, /* Reg 8bh */
{REG_CRTTV_INK_CURS_RED1 ,0x1f}, /* Reg 8ch */
{REG_CRTTV_INK_CURS_FIFO ,0x00}, /* Reg 8eh */
{REG_BITBLT_CTRL0 ,0x00}, /* Reg 100h */
{REG_BITBLT_CTRL1 ,0x00}, /* Reg 101h */
{REG_BITBLT_ROP_CODE ,0x00}, /* Reg 102h */
{REG_BITBLT_OPERATION ,0x00}, /* Reg 103h */
{REG_BITBLT_SRC_START_ADDR0 ,0x00}, /* Reg 104h */
{REG_BITBLT_SRC_START_ADDR1 ,0x00}, /* Reg 105h */
{REG_BITBLT_SRC_START_ADDR2 ,0x00}, /* Reg 106h */
{REG_BITBLT_DEST_START_ADDR0 ,0x00}, /* Reg 108h */
{REG_BITBLT_DEST_START_ADDR1 ,0x00}, /* Reg 109h */
{REG_BITBLT_DEST_START_ADDR2 ,0x00}, /* Reg 10ah */
{REG_BITBLT_MEM_ADDR_OFFSET0 ,0x00}, /* Reg 10ch */
{REG_BITBLT_MEM_ADDR_OFFSET1 ,0x00}, /* Reg 10dh */
{REG_BITBLT_WIDTH0 ,0x00}, /* Reg 110h */
{REG_BITBLT_WIDTH1 ,0x00}, /* Reg 111h */
{REG_BITBLT_HEIGHT0 ,0x00}, /* Reg 112h */
{REG_BITBLT_HEIGHT1 ,0x00}, /* Reg 113h */
{REG_BITBLT_BACKGND_COLOR0 ,0x00}, /* Reg 114h */
{REG_BITBLT_BACKGND_COLOR1 ,0x00}, /* Reg 115h */
{REG_BITBLT_FOREGND_COLOR0 ,0x00}, /* Reg 118h */
{REG_BITBLT_FOREGND_COLOR1 ,0x00}, /* Reg 119h */
{REG_LUT_MODE ,0x00}, /* Reg 1e0h */
{REG_LUT_ADDR ,0x00}, /* Reg 1e2h */
{REG_LUT_DATA ,0x00}, /* Reg 1e4h */
{REG_PWR_SAVE_CFG ,0x00}, /* Reg 1f0h */
{REG_PWR_SAVE_STATUS ,0x00}, /* Reg 1f1h */
{REG_CPU2MEM_WATCHDOG ,0x00}, /* Reg 1f4h */
{REG_DISPLAY_MODE ,0x02}, /* Reg 1fch */
{FINISHED_REG_CFG, 0x00}
},
25175, /* ClkI (kHz) */
14318, /* ClkI2 (kHz) */
40000, /* Bus Clock (kHz) */
0x00000000, /* Registers */
0x00000000, /* Display Memory */
60, /* Panel Frame Rate (Hz) */
60, /* CRT Frame Rate (Hz) */
50, /* Memory speed (ns) */
8000, /* Memory refresh time (us) */
84, /* Trc: Ras to Cas Delay (ns) */
30, /* Trp: Ras Precharge time (ns) */
50, /* Tras: Ras Pulse Width time in ns */
50, /* Trac: Ras Access Charge time (ns) */
TRUE /* Enable TV flicker filter */
};
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