/*===========================================================================
**  HAL_REGS.H 
**---------------------------------------------------------------------------
** Copyright (c) 1997, 2001 Epson Research and Development, Inc.
** All Rights Reserved.
===========================================================================*/

#ifndef __HAL_REGS_H__
#define __HAL_REGS_H__

/*
** 13506 register names
*/

#define REG_REVISION_CODE              0x00
#define REG_MISC                       0x01
#define REG_GPIO_CONFIG                0x04
#define REG_GPIO_CTRL                  0x08
#define REG_MD_CFG_STATUS0             0x0c
#define REG_MD_CFG_STATUS1             0x0d
#define REG_MEM_CLOCK_CFG              0x10
#define REG_LCD_PCLK_CFG               0x14
#define REG_CRTTV_PCLK_CFG             0x18
#define REG_MPCLK_CFG                  0x1c
#define REG_CPU2MEM_WAIT_SEL           0x1e
#define REG_MEM_CFG                    0x20
#define REG_DRAM_REFRESH               0x21
#define REG_DRAM_TIMINGS_CTRL0         0x2a
#define REG_DRAM_TIMINGS_CTRL1         0x2b
#define REG_PANEL_TYPE                 0x30
#define REG_MOD_RATE                   0x31
#define REG_LCD_HDP                    0x32
#define REG_LCD_HNDP                   0x34
#define REG_TFT_FPLINE_START           0x35
#define REG_TFT_FPLINE_PULSE           0x36
#define REG_LCD_VDP0                   0x38
#define REG_LCD_VDP1                   0x39
#define REG_LCD_VNDP                   0x3a
#define REG_TFT_FPFRAME_START          0x3b
#define REG_TFT_FPFRAME_PULSE          0x3c
#define REG_LCD_LINE_COUNT0            0x3e
#define REG_LCD_LINE_COUNT1            0x3f
#define REG_LCD_DISPLAY_MODE           0x40
#define REG_LCD_MISC                   0x41
#define REG_LCD_START_ADDR0            0x42
#define REG_LCD_START_ADDR1            0x43
#define REG_LCD_START_ADDR2            0x44
#define REG_LCD_MEM_ADDR_OFFSET0       0x46
#define REG_LCD_MEM_ADDR_OFFSET1       0x47
#define REG_LCD_PIXEL_PANNING          0x48
#define REG_LCD_FIFO_HIGH_THRESHOLD    0x4a
#define REG_LCD_FIFO_LOW_THRESHOLD     0x4b
#define REG_CRTTV_HDP                  0x50
#define REG_CRTTV_HNDP                 0x52
#define REG_CRTTV_HRTC_START           0x53
#define REG_CRT_HRTC_PULSE             0x54
#define REG_CRTTV_VDP0                 0x56
#define REG_CRTTV_VDP1                 0x57
#define REG_CRTTV_VNDP                 0x58
#define REG_CRTTV_VRTC_START           0x59
#define REG_CRT_VRTC_PULSE             0x5a
#define REG_TV_OUTPUT_CTRL             0x5b
#define REG_CRTTV_LINE_COUNT0          0x5e
#define REG_CRTTV_LINE_COUNT1          0x5f
#define REG_CRTTV_DISPLAY_MODE         0x60
#define REG_CRTTV_START_ADDR0          0x62
#define REG_CRTTV_START_ADDR1          0x63
#define REG_CRTTV_START_ADDR2          0x64
#define REG_CRTTV_MEM_ADDR_OFFSET0     0x66
#define REG_CRTTV_MEM_ADDR_OFFSET1     0x67
#define REG_CRTTV_PIXEL_PANNING        0x68
#define REG_CRTTV_FIFO_HIGH_THRESHOLD  0x6a
#define REG_CRTTV_FIFO_LOW_THRESHOLD   0x6b
#define REG_LCD_INK_CURS_CTRL          0x70
#define REG_LCD_INK_CURS_START_ADDR    0x71
#define REG_LCD_CURSOR_X_POS0          0x72
#define REG_LCD_CURSOR_X_POS1          0x73
#define REG_LCD_CURSOR_Y_POS0          0x74
#define REG_LCD_CURSOR_Y_POS1          0x75
#define REG_LCD_INK_CURS_BLUE0         0x76
#define REG_LCD_INK_CURS_GREEN0        0x77
#define REG_LCD_INK_CURS_RED0          0x78
#define REG_LCD_INK_CURS_BLUE1         0x7a
#define REG_LCD_INK_CURS_GREEN1        0x7b
#define REG_LCD_INK_CURS_RED1          0x7c
#define REG_LCD_INK_CURS_FIFO          0x7e
#define REG_CRTTV_INK_CURS_CTRL        0x80
#define REG_CRTTV_INK_CURS_START_ADDR  0x81
#define REG_CRTTV_CURSOR_X_POS0        0x82
#define REG_CRTTV_CURSOR_X_POS1        0x83
#define REG_CRTTV_CURSOR_Y_POS0        0x84
#define REG_CRTTV_CURSOR_Y_POS1        0x85
#define REG_CRTTV_INK_CURS_BLUE0       0x86
#define REG_CRTTV_INK_CURS_GREEN0      0x87
#define REG_CRTTV_INK_CURS_RED0        0x88
#define REG_CRTTV_INK_CURS_BLUE1       0x8a
#define REG_CRTTV_INK_CURS_GREEN1      0x8b
#define REG_CRTTV_INK_CURS_RED1        0x8c
#define REG_CRTTV_INK_CURS_FIFO        0x8e
#define REG_BITBLT_CTRL0               0x100
#define REG_BITBLT_CTRL1               0x101
#define REG_BITBLT_ROP_CODE            0x102
#define REG_BITBLT_OPERATION           0x103
#define REG_BITBLT_SRC_START_ADDR0     0x104
#define REG_BITBLT_SRC_START_ADDR1     0x105
#define REG_BITBLT_SRC_START_ADDR2     0x106
#define REG_BITBLT_DEST_START_ADDR0    0x108
#define REG_BITBLT_DEST_START_ADDR1    0x109
#define REG_BITBLT_DEST_START_ADDR2    0x10a
#define REG_BITBLT_MEM_ADDR_OFFSET0    0x10c
#define REG_BITBLT_MEM_ADDR_OFFSET1    0x10d
#define REG_BITBLT_WIDTH0              0x110
#define REG_BITBLT_WIDTH1              0x111
#define REG_BITBLT_HEIGHT0             0x112
#define REG_BITBLT_HEIGHT1             0x113
#define REG_BITBLT_BACKGND_COLOR0      0x114
#define REG_BITBLT_BACKGND_COLOR1      0x115
#define REG_BITBLT_FOREGND_COLOR0      0x118
#define REG_BITBLT_FOREGND_COLOR1      0x119
#define REG_LUT_MODE                   0x1e0
#define REG_LUT_ADDR                   0x1e2
#define REG_LUT_DATA                   0x1e4
#define REG_PWR_SAVE_CFG               0x1f0
#define REG_PWR_SAVE_STATUS            0x1f1
#define REG_CPU2MEM_WATCHDOG           0x1f4
#define REG_DISPLAY_MODE               0x1fc
#define REG_MEDIAPLUG_LCMD             0x1000
#define REG_MEDIAPLUG_RESERVED_LCMD    0x1002
#define REG_MEDIAPLUG_CMD              0x1004
#define REG_MEDIAPLUG_RESERVED_CMD     0x1006
#define REG_MEDIAPLUG_DATA             0x1008

/*
** In total, there are 123 bytes of registers.
** For initialization, reserve 150 bytes for registers.
*/
#define MAX_REG    150


/*
** Highest reg is the highest register address.
*/
#define HIGHEST_REG    REG_MEDIAPLUG_DATA


/*
** Indicate that register definitions are finished in appcfg.h
*/
#define FINISHED_REG_CFG    0xffff


#endif      /*  __HAL_REGS_H__ */