?? 優龍論壇-arm_ini文件分析及實例_1.htm
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0x00000000<BR> EXTDBWTH 0x3010
R/W Data bus width for each memory bank
0x00000000<BR> ROMCON0 0x3014
R/W ROM/SRAM/Flash bank0 control register 0x00000060<BR>
ROMCON1 0x3018 R/W
ROM/SRAM/Flash bank1 control register 0x00000060<BR>
ROMCON2 0x301c R/W
ROM/SRAM/Flash bank2 control register 0x00000060<BR>
ROMCON3 0x3020 R/W
ROM/SRAM/Flash bank3 control register 0x00000060<BR>
ROMCON4 0x3024 R/W
ROM/SRAM/Flash bank4 control register 0x00000060<BR>
ROMCON5 0x3028 R/W
ROM/SRAM/Flash bank5 control register 0x00000060<BR> DRAMCON0
0x302c R/W DRAM bank0 control
register
0x00000000<BR> DRAMCON1 0x3030
R/W DRAM bank1 control
register
0x00000000<BR> DRAMCON2 0x3034
R/W DRAM bank2 control
register
0x00000000<BR> DRAMCON3 0x3038
R/W DRAM bank3 control
register
0x00000000<BR> REFEXTCON 0x303c R/W
Refresh and external I/O control register
0x000083FD<BR>2.SYSCFG的設置(0x3ff0000)
0xE7ffff90<BR> 1110 0111 1111 1111 1111 1111
1001 0000<BR> bit0 = stall enable ( SE ) <BR>必須設置為0<BR> bit1 =
cache enable( CE )<BR>設置為0時，表示不允許cache 操作<BR> bit2 = Write buffer
enable( WE )<BR> 設置為0時，表示不允許寫緩沖操作<BR>
bit3 = 0<BR> bit[5:4] = cache mode( CM )<BR>
設置為01 , 0Kbyte SRAM 8Kbyte cache<BR> bit[15:6] = Internal SRAM base
pointer<BR> 得到地址指針3FE0000<BR> bit[25:16] =
Special register bank base pointer<BR>
得到地址指針3FF0000<BR> bit[30:26] = Product Identifier( PD_ID
)<BR> 11001 = S3C4510B<BR> bit[31] = Sync
DRAM Mode( SDM )<BR> 設置1= Sync DRAM interface for
4 SRAM banks<BR>3.EXTDBWTH的設置(0x3ff3010)
0x3009<BR> 0000 0000 0000 0000 0011 0000 0000
1001<BR> bit[1:0] = Data bus width for ROM/SRAM/FLASH
bank 0(DSR0)<BR> 01 = 8bits(
ROM是8位數據總線)<BR> bit[3:2] = Data bus width for
ROM/SRAM/FLASH bank 1(DSR1)<BR> 10 =
16bits( FLASH是16位數據總線)<BR> bit[5:4]DSR2, bit[7:6] DSR3,
[9:8] DSR4, [11:10] DSR5<BR> 00 =
disable<BR> bit[13:12] = Date bus width for DRAM bank 0
( DSD0 )<BR> 11 = 32bits(
SDRAM是32位數據總線)<BR>bit[15:14]DSD1, bit[17:16]DSD2,
bit[19:18]DSD3<BR> 00 = Disable<BR>bit[21:20] = Data bus width
for external I/O bank 0( DSX0 )<BR> bit[23:22]DSX1, bit[25:24]DSX2,
bit[27:26]DSX3<BR>00 = Disable<BR>bit[31:28] =
0<BR>4.ROMCON0的設置(0x3ff3014)
0x12040060<BR> 0001 0010 0000 0100 0000 0000 0110
0000<BR>bit[1:0] = Page mode configuration( PMC )<BR> 00 = Normal
ROM<BR> bit[3:2] = Page address access time( tPA
)<BR> 00 = 5 cycles<BR>
bit[6:4] = Programmable access cycles( tACC
)<BR> 110 = 7 cycles<BR>
bit[9:7] = 0<BR> bit[19:10] = ROM/SRAM/FLASH Bank0 Base
Pointer<BR> 0x100
0000<BR> bit[29:20] = ROM/SRAM/FLASH Bank0 Next
Pointer<BR> 0x120
0000<BR> bit[31:30] =
0<BR>5.ROMCON1的設置(0x3ff3018)
0x14048060<BR> 0001 0100 0000 0100 1000 0000 0110
0000<BR>bit[1:0] = Page mode configuration( PMC )<BR> 00 = Normal
ROM<BR> bit[3:2] = Page address access time( tPA
)<BR> 00 = 5 cycles<BR>
bit[6:4] = Programmable access cycles( tACC
)<BR> 110 = 7 cycles<BR>
bit[9:7] = 0<BR> bit[19:10] = ROM/SRAM/FLASH Bank0 Base
Pointer<BR> 0x120
0000<BR> bit[29:20] = ROM/SRAM/FLASH Bank0 Next
Pointer<BR> 0x140
0000<BR> bit[31:30] =
0<BR>6.ROMCON2的設置(0x3ff301c)
0x16050060<BR> 0001 0110 0000 0101 0000 0000 0110
0000<BR>bit[1:0] = Page mode configuration( PMC )<BR> 00 = Normal
ROM<BR> bit[3:2] = Page address access time( tPA
)<BR> 00 = 5 cycles<BR>
bit[6:4] = Programmable access cycles( tACC
)<BR> 110 = 7 cycles<BR>
bit[9:7] = 0<BR> bit[19:10] = ROM/SRAM/FLASH Bank0 Base
Pointer<BR> 0x140
0000<BR> bit[29:20] = ROM/SRAM/FLASH Bank0 Next
Pointer<BR> 0x160
0000<BR> bit[31:30] =
0<BR>7.ROMCON3的設置(0x3ff3020)
0x18058060<BR> 0001 1000 0000 0101 1000 0000 0110
0000<BR>bit[1:0] = Page mode configuration( PMC )<BR> 00 = Normal
ROM<BR> bit[3:2] = Page address access time( tPA
)<BR> 00 = 5 cycles<BR>
bit[6:4] = Programmable access cycles( tACC
)<BR> 110 = 7 cycles<BR>
bit[9:7] = 0<BR> bit[19:10] = ROM/SRAM/FLASH Bank0 Base
Pointer<BR> 0x160
0000<BR> bit[29:20] = ROM/SRAM/FLASH Bank0 Next
Pointer<BR> 0x180
0000<BR> bit[31:30] = 0<BR>
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vAlign=center>-- 作者：bob3000<BR>-- 發布時間：2004-3-30
18:09:01<BR><BR>-- <BR>8.ROMCON4的設置(0x3ff3024)
0x1a060060<BR> 0001 1010 0000 0110 0000 0000 0110
0000<BR>bit[1:0] = Page mode configuration( PMC )<BR> 00 = Normal
ROM<BR> bit[3:2] = Page address access time( tPA
)<BR> 00 = 5 cycles<BR>
bit[6:4] = Programmable access cycles( tACC
)<BR> 110 = 7 cycles<BR>
bit[9:7] = 0<BR> bit[19:10] = ROM/SRAM/FLASH Bank0 Base
Pointer<BR> 0x180
0000<BR> bit[29:20] = ROM/SRAM/FLASH Bank0 Next
Pointer<BR> 0x1a0
0000<BR> bit[31:30] =
0<BR>9.ROMCON5的設置(0x3ff3028)
0x1a068060<BR> 0001 1010 0000 0110 1000 0000 0110
0000<BR>bit[1:0] = Page mode configuration( PMC )<BR> 00 = Normal
ROM<BR> bit[3:2] = Page address access time( tPA
)<BR> 00 = 5 cycles<BR>
bit[6:4] = Programmable access cycles( tACC
)<BR> 110 = 7 cycles<BR>
bit[9:7] = 0<BR> bit[19:10] = ROM/SRAM/FLASH Bank0 Base
Pointer<BR> 0x1a0
0000<BR> bit[29:20] = ROM/SRAM/FLASH Bank0 Next
Pointer<BR> 0x1c0
0000<BR> bit[31:30] =
0<BR>10.DRAMCON0的設置(0x3ff302c)
0x04000380<BR> 0000 0100 0000 0000 0000 0011 1000
0000<BR> bit[0] = EDO mode(EDO)<BR>
0=正常DRAM( Fast page mode DRAM )<BR> bit[2:1] = CAS strobe
time( tCS )<BR> 00 = 1 cycle<BR>
bit[3] = CAS pre-charge time( tCP )<BR> 0 = 1
cycle<BR> bit[6:4] = 保留<BR> bit[7] = RAS to CAS
delay( tRC or tRCD )<BR> 1 = 2
cycles<BR> bit[9:8] = RAS pre-charge time( tRP
)<BR> 11 = 4 cycles<BR>
bit[19:10] = DRAM Bank0 Base Pointer<BR>0x0<BR> bit[29:20] =
DRAM Bank 0 Next Pointer<BR> 0x040
0000<BR> bit[31:30] = CAN<BR> 00 = 8
bits<BR>11.DRAMCON1的設置(0x3ff3030)
0x06010380<BR> 0000 0110 0000 0001 0000 0011 1000
0000<BR> bit[0] = EDO mode(EDO)<BR>
0=正常DRAM( Fast page mode DRAM )<BR> bit[2:1] = CAS strobe
time( tCS )<BR> 00 = 1 cycle<BR>
bit[3] = CAS pre-charge time( tCP )<BR> 0 = 1
cycle<BR> bit[6:4] = 保留<BR> bit[7] = RAS to CAS
delay( tRC or tRCD )<BR> 1 = 2
cycles<BR> bit[9:8] = RAS pre-charge time( tRP
)<BR> 11 = 4 cycles<BR>
bit[19:10] = DRAM Bank0 Base Pointer<BR>0x040 0000<BR>
bit[29:20] = DRAM Bank 0 Next Pointer<BR> 0x060
0000<BR> bit[31:30] = CAN<BR> 00 = 8
bits<BR>12.DRAMCON2的設置(0x3ff3034)
0x08018380<BR> 0000 1000 0000 0001 1000 0011 1000
0000<BR> bit[0] = EDO mode(EDO)<BR>
0=正常DRAM( Fast page mode DRAM )<BR> bit[2:1] = CAS strobe
time( tCS )<BR> 00 = 1 cycle<BR>
bit[3] = CAS pre-charge time( tCP )<BR> 0 = 1
cycle<BR> bit[6:4] = 保留<BR> bit[7] = RAS to CAS
delay( tRC or tRCD )<BR> 1 = 2
cycles<BR> bit[9:8] = RAS pre-charge time( tRP
)<BR> 11 = 4 cycles<BR>
bit[19:10] = DRAM Bank0 Base Pointer<BR>0x060 0000<BR>
bit[29:20] = DRAM Bank 0 Next Pointer<BR> 0x080
0000<BR> bit[31:30] = CAN<BR> 00 = 8
bits<BR>13.DRAMCON3的設置(0x3ff3038)
0x0a020380<BR> 0000 1010 0000 0010 0000 0011 1000
0000<BR> bit[0] = EDO mode(EDO)<BR>
0=正常DRAM( Fast page mode DRAM )<BR> bit[2:1] = CAS strobe
time( tCS )<BR> 00 = 1 cycle<BR>
bit[3] = CAS pre-charge time( tCP )<BR> 0 = 1
cycle<BR> bit[6:4] = 保留<BR> bit[7] = RAS to CAS
delay( tRC or tRCD )<BR> 1 = 2
cycles<BR> bit[9:8] = RAS pre-charge time( tRP
)<BR> 11 = 4 cycles<BR>
bit[19:10] = DRAM Bank0 Base Pointer<BR>0x080 0000<BR>
bit[29:20] = DRAM Bank 0 Next Pointer<BR> 0x0a0
0000<BR> bit[31:30] = CAN<BR> 00 = 8
bits<BR>14.REFEXTCON的設置(0x3ff303c) 0xce338360<BR>1100 1110
0011 0011 1000 0011 0110 0000<BR> DRAM
刷新和外部I/O控制寄存器<BR> bit[9:0] = External I/O bank0 base
pointer<BR> 0x360 0000<BR> bit[14:10]
= 0<BR> bit[15] = Validity of special register
field(VSF)<BR> 1 = 可以存取memory bank<BR>
bit[16] = 允許刷新(REN)<BR> 1 =
允許DRAM刷新<BR> bit[19:17] = CAS hold time( tCHR )
ROW cycle time( tRC )<BR> 001 = 2
cycles<BR> bit[20] = CAS 設置時間( tCSR )<BR>1 = 2
cycles<BR> bit [31:21] = 刷新計數值<BR>
0x11001110001 = 0x671<BR>配置好后，加載一個點燈程序就可以在ARM板上跑起來了。<BR><BR>
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vAlign=center>-- 作者：bob3000<BR>-- 發布時間：2004-3-30
18:10:16<BR><BR>-- <BR>不過有些細節我也還不清楚，希望大家一起來討論<BR>歡迎交流<BR>我的qq:12665590
<BR> mail: bobzhu2002@yahoo.com.cn
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vAlign=center>-- 作者：samsun<BR>-- 發布時間：2004-3-30
23:36:46<BR><BR>-- <BR>歡迎 bob3000在本版多發貼交流！
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vAlign=center>-- 作者：ucdragon<BR>-- 發布時間：2004-3-31
16:05:11<BR><BR>-- <BR>不錯啊，bob3000 ！
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