/* $Id: ultra.S,v 1.70.2.1 2002/03/03 10:31:56 davem Exp $ * ultra.S: Don't expand these all over the place... * * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com) */#include <linux/config.h>#include <asm/asi.h>#include <asm/pgtable.h>#include <asm/page.h>#include <asm/spitfire.h>#include <asm/mmu_context.h>#include <asm/pil.h>#include <asm/head.h>	/* Basically, most of the Spitfire vs. Cheetah madness	 * has to do with the fact that Cheetah does not support	 * IMMU flushes out of the secondary context.  Someone needs	 * to throw a south lake birthday party for the folks	 * in Microelectronics who refused to fix this shit.	 */	/* This file is meant to be read efficiently by the CPU, not humans.	 * Staraj sie tego nikomu nie pierdolnac...	 */	.text	.align		32	.globl		__flush_tlb_page, __flush_tlb_mm, __flush_tlb_range__flush_tlb_page: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=page&PAGE_MASK, %o2=SECONDARY_CONTEXT */	ldxa		[%o2] ASI_DMMU, %g2	cmp		%g2, %o0	bne,pn		%icc, __spitfire_flush_tlb_page_slow	 or		%o1, 0x10, %g3	stxa		%g0, [%g3] ASI_DMMU_DEMAP	stxa		%g0, [%g3] ASI_IMMU_DEMAP	retl	 flush		%g6	nop	nop	nop	nop	nop	nop	nop	nop__flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */	ldxa		[%o1] ASI_DMMU, %g2	cmp		%g2, %o0	bne,pn		%icc, __spitfire_flush_tlb_mm_slow	 mov		0x50, %g3	stxa		%g0, [%g3] ASI_DMMU_DEMAP	stxa		%g0, [%g3] ASI_IMMU_DEMAP	retl	 flush		%g6	nop	nop	nop	nop	nop	nop	nop	nop__flush_tlb_range: /* %o0=(ctx&TAG_CONTEXT_BITS), %o1=start&PAGE_MASK, %o2=SECONDARY_CONTEXT,		    * %o3=end&PAGE_MASK, %o4=PAGE_SIZE, %o5=(end - start)		    */#define TLB_MAGIC	207 /* Students, do you know how I calculated this?  -DaveM */	cmp		%o5, %o4	bleu,pt		%xcc, __flush_tlb_page	 srlx		%o5, PAGE_SHIFT, %g5	cmp		%g5, TLB_MAGIC	bgeu,pn		%icc, __spitfire_flush_tlb_range_constant_time	 or		%o1, 0x10, %g5	ldxa		[%o2] ASI_DMMU, %g2	cmp		%g2, %o0__spitfire_flush_tlb_range_page_by_page:	bne,pn		%icc, __spitfire_flush_tlb_range_pbp_slow	 sub		%o5, %o4, %o51:	stxa		%g0, [%g5 + %o5] ASI_DMMU_DEMAP	stxa		%g0, [%g5 + %o5] ASI_IMMU_DEMAP	brnz,pt		%o5, 1b	 sub		%o5, %o4, %o5	retl	 flush		%g6__spitfire_flush_tlb_range_constant_time: /* %o0=ctx, %o1=start, %o3=end */	rdpr		%pstate, %g1	wrpr		%g1, PSTATE_IE, %pstate	mov		TLB_TAG_ACCESS, %g3	mov		((SPITFIRE_HIGHEST_LOCKED_TLBENT-1) << 3), %g2	/* Spitfire Errata #32 workaround. */	mov		0x8, %o4	stxa		%g0, [%o4] ASI_DMMU	flush		%g61:	ldxa		[%g2] ASI_ITLB_TAG_READ, %o4	and		%o4, TAG_CONTEXT_BITS, %o5	cmp		%o5, %o0	bne,pt		%icc, 2f	 andn		%o4, TAG_CONTEXT_BITS, %o4	cmp		%o4, %o1	blu,pt		%xcc, 2f	 cmp		%o4, %o3	blu,pn		%xcc, 4f2:	 ldxa		[%g2] ASI_DTLB_TAG_READ, %o4	and		%o4, TAG_CONTEXT_BITS, %o5	cmp		%o5, %o0	andn		%o4, TAG_CONTEXT_BITS, %o4	bne,pt		%icc, 3f	 cmp		%o4, %o1	blu,pt		%xcc, 3f	 cmp		%o4, %o3	blu,pn		%xcc, 5f	 nop3:	brnz,pt		%g2, 1b	 sub		%g2, (1 << 3), %g2	retl	 wrpr		%g1, 0x0, %pstate4:	stxa		%g0, [%g3] ASI_IMMU	stxa		%g0, [%g2] ASI_ITLB_DATA_ACCESS	flush		%g6	/* Spitfire Errata #32 workaround. */	mov		0x8, %o4	stxa		%g0, [%o4] ASI_DMMU	flush		%g6	ba,pt		%xcc, 2b	 nop5:	stxa		%g0, [%g3] ASI_DMMU	stxa		%g0, [%g2] ASI_DTLB_DATA_ACCESS	flush		%g6	/* Spitfire Errata #32 workaround. */	mov		0x8, %o4	stxa		%g0, [%o4] ASI_DMMU	flush		%g6	ba,pt		%xcc, 3b	 nop__spitfire_flush_tlb_mm_slow:	rdpr		%pstate, %g1	wrpr		%g1, PSTATE_IE, %pstate	stxa		%o0, [%o1] ASI_DMMU	stxa		%g0, [%g3] ASI_DMMU_DEMAP	stxa		%g0, [%g3] ASI_IMMU_DEMAP	flush		%g6	stxa		%g2, [%o1] ASI_DMMU	flush		%g6	retl	 wrpr		%g1, 0, %pstate__spitfire_flush_tlb_page_slow:	rdpr		%pstate, %g1	wrpr		%g1, PSTATE_IE, %pstate	stxa		%o0, [%o2] ASI_DMMU	stxa		%g0, [%g3] ASI_DMMU_DEMAP	stxa		%g0, [%g3] ASI_IMMU_DEMAP	flush		%g6	stxa		%g2, [%o2] ASI_DMMU	flush		%g6	retl	 wrpr		%g1, 0, %pstate__spitfire_flush_tlb_range_pbp_slow:	rdpr		%pstate, %g1	wrpr		%g1, PSTATE_IE, %pstate	stxa		%o0, [%o2] ASI_DMMU2:	stxa		%g0, [%g5 + %o5] ASI_DMMU_DEMAP	stxa		%g0, [%g5 + %o5] ASI_IMMU_DEMAP	brnz,pt		%o5, 2b	 sub		%o5, %o4, %o5	flush		%g6	stxa		%g2, [%o2] ASI_DMMU	flush		%g6	retl	 wrpr		%g1, 0x0, %pstate/* * The following code flushes one page_size worth. */#if (PAGE_SHIFT == 13)#define ITAG_MASK 0xfe#elif (PAGE_SHIFT == 16)#define ITAG_MASK 0x7fe#else#error unsupported PAGE_SIZE#endif	.align		32	.globl		__flush_icache_page__flush_icache_page:	/* %o0 = phys_page */	sethi		%hi(1 << 13), %o2	! IC_set bit	mov		1, %g1	srlx		%o0, 5, %o0	clr		%o1			! IC_addr	sllx		%g1, 36, %g1	ldda		[%o1] ASI_IC_TAG, %o4	sub		%g1, 1, %g2	or		%o0, %g1, %o0		! VALID+phys-addr comparitor	sllx		%g2, 1, %g2	andn		%g2, ITAG_MASK, %g2	! IC_tag mask	nop	nop	nop	nop	nop	nop1:	addx		%g0, %g0, %g0	ldda		[%o1 + %o2] ASI_IC_TAG, %g4	addx		%g0, %g0, %g0	and		%o5, %g2, %g3	cmp		%g3, %o0	add		%o1, 0x20, %o1	ldda		[%o1] ASI_IC_TAG, %o4	be,pn		%xcc, iflush12:	 nop	and		%g5, %g2, %g5	cmp		%g5, %o0	be,pn		%xcc, iflush23:	 cmp		%o1, %o2	bne,pt		%xcc, 1b	 addx		%g0, %g0, %g0	nop	sethi		%uhi(PAGE_OFFSET), %g4	retl	 sllx		%g4, 32, %g4iflush1:sub		%o1, 0x20, %g3	stxa		%g0, [%g3] ASI_IC_TAG	flush		%g6	ba,a,pt		%xcc, 2biflush2:sub		%o1, 0x20, %g3	stxa		%g0, [%o1 + %o2] ASI_IC_TAG	flush		%g6	ba,a,pt		%xcc, 3b#if (PAGE_SHIFT == 13)#define DTAG_MASK 0x3#elif (PAGE_SHIFT == 16)#define DTAG_MASK 0x1f#elif (PAGE_SHIFT == 19)#define DTAG_MASK 0xff#elif (PAGE_SHIFT == 22)#define DTAG_MASK 0x3ff#endif	.align		64	.globl		__flush_dcache_page__flush_dcache_page:	/* %o0=kaddr, %o1=flush_icache */	sub		%o0, %g4, %o0	clr		%o4	srlx		%o0, 11, %o0	sethi		%hi(1 << 14), %o21:	ldxa		[%o4] ASI_DCACHE_TAG, %o3	! LSU	Group	add		%o4, (1 << 5), %o4		! IEU0	ldxa		[%o4] ASI_DCACHE_TAG, %g1	! LSU	Group	add		%o4, (1 << 5), %o4		! IEU0	ldxa		[%o4] ASI_DCACHE_TAG, %g2	! LSU	Group	o3 available	add		%o4, (1 << 5), %o4		! IEU0	andn		%o3, DTAG_MASK, %o3		! IEU1	ldxa		[%o4] ASI_DCACHE_TAG, %g3	! LSU	Group	add		%o4, (1 << 5), %o4		! IEU0	andn		%g1, DTAG_MASK, %g1		! IEU1	cmp		%o0, %o3			! IEU1	Group	be,a,pn		%xcc, dflush1			! CTI	 sub		%o4, (4 << 5), %o4		! IEU0	(Group)	cmp		%o0, %g1			! IEU1	Group	andn		%g2, DTAG_MASK, %g2		! IEU0	be,a,pn		%xcc, dflush2			! CTI	 sub		%o4, (3 << 5), %o4		! IEU0	(Group)	cmp		%o0, %g2			! IEU1	Group	andn		%g3, DTAG_MASK, %g3		! IEU0	be,a,pn		%xcc, dflush3			! CTI	 sub		%o4, (2 << 5), %o4		! IEU0	(Group)	cmp		%o0, %g3			! IEU1	Group	be,a,pn		%xcc, dflush4			! CTI	 sub		%o4, (1 << 5), %o4		! IEU02:	cmp		%o4, %o2			! IEU1	Group	bne,pt		%xcc, 1b			! CTI	 nop						! IEU0	/* The I-cache does not snoop local stores so we	 * better flush that too when necessary.	 */	brnz,pt		%o1, __flush_icache_page	 sllx		%o0, 11, %o0	retl	 nopdflush1:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4dflush2:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4dflush3:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4dflush4:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4	membar		#Sync	ba,pt		%xcc, 2b	 nop	.align		32__prefill_dtlb:	rdpr		%pstate, %g7	wrpr		%g7, PSTATE_IE, %pstate	mov		TLB_TAG_ACCESS, %g1	stxa		%o0, [%g1] ASI_DMMU	stxa		%o1, [%g0] ASI_DTLB_DATA_IN	flush		%g6	retl	 wrpr		%g7, %pstate__prefill_itlb:	rdpr		%pstate, %g7	wrpr		%g7, PSTATE_IE, %pstate	mov		TLB_TAG_ACCESS, %g1	stxa		%o0, [%g1] ASI_IMMU	stxa		%o1, [%g0] ASI_ITLB_DATA_IN	flush		%g6	retl	 wrpr		%g7, %pstate	.globl		__update_mmu_cache__update_mmu_cache:	/* %o0=vma, %o1=address, %o2=pte */	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fault_code], %o3	srlx		%o1, PAGE_SHIFT, %o1	ldx		[%o0 + 0x0], %o4		/* XXX vma->vm_mm */	brz,pn		%o3, 1f	 sllx		%o1, PAGE_SHIFT, %o0	ldx		[%o4 + AOFF_mm_context], %o5	andcc		%o3, FAULT_CODE_DTLB, %g0	mov		%o2, %o1	and		%o5, TAG_CONTEXT_BITS, %o5	bne,pt		%xcc, __prefill_dtlb	 or		%o0, %o5, %o0	ba,a,pt		%xcc, __prefill_itlb1:	retl	 nop	/* Cheetah specific versions, patched at boot time.  */__cheetah_flush_tlb_page: /* 14 insns */	rdpr		%pstate, %g5	andn		%g5, PSTATE_IE, %g2	wrpr		%g2, 0x0, %pstate	wrpr		%g0, 1, %tl