?? bwmeter.lst
字號:
A51 MACRO ASSEMBLER BWMETER 06/05/2002 14:07:37 PAGE 1
MACRO ASSEMBLER A51 V6.01
OBJECT MODULE PLACED IN .\BWmeter.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE .\BWmeter.A51 SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ;--------------------------------------------------------------------------
2 ; BWmeter.A51 2-07-02 LTH
3 ;
4 ; A USB 2.0 High-Speed (480 Mbits/sec) bandwidth meter.
5 ;
6 ; Serves as endless, no-wait, source and sink of bulk packets. Measures the
7 ; number of packets delivered/consumed by the host per microframe.
8 ;
9 ; Correct operation can be determined by glancing at the four FX2 Dev Board LEDs:
10 ; L1 L2 L3 L4
11 ; ON ON ON OFF
12 ;
13 ; L1 is ON for USB high-speed operation (off for full-speed). Indicates you're connected
14 ; to a full-speed host, and the USB host driver is working.
15 ; L2-L3 toggle once per SOF, proving that the code is running.
16 ; L4 comes on only if the code causes any USB NAK's (was used for debug only).
17 ;
18 ; Endpoints used:
19 ; EP1: Bulk IN 64 bytes (retrieves packet buffer history, displays in control panel)
20 ; EP2, EP4: Bulk OUT, double-buffered 512 bytes (endless data sink)
21 ; EP6, EP8: Bulk IN, double-buffered 512 bytes (endliss data source)
22 ;
23 ; NOTE: By using these FX2 default endpoints for Interface 0/Alt Setting 1,
24 ; no USB enumeration code is required.
25 ;
26 ; Registers used:
27 ; r0 is pointer to 64-byte buffer that holds packets-per-frame (ppf) history
28 ; dptr used as a data transfer pointer
29 ;
30 ; Operating Instructions:
31 ;
32 ; 1. Plug in board, load Cypress USB EzMr application (Control Panel).
33 ; 2. Check LED1 (D5) for ON, indicating high-speed operation. If not, go to 3a.
34 ; 3. LED2 and LED3 (D4-D3) should both be on, indicating receipt of SOF packets.
35 ; 3a. Check the port, driver, software, BIOS, etc.
36 ; 4. Click 'Set Iface', then 'Get Pipes' buttons. (Sets the default Interface 0/AltSetti
ng 1).
37 ; 4a. If you don't see the 5 pipes, 0-5, go to 3a.
38 ; 5. Set up a bulk transfer: EP8-IN (default), type 8192 in LENGTH box. [can also use EP
6-IN]
39 ; 6. Click BulkTrans. *** You should see the screen fill with blocks of 0's and 1's.
40 ; NOTE: The 'ping' buffer has 0's, the 'pong' buffer has 1's. Last byte shows number
of IN's.
41 ; *** The 7-seg readout leaps to life, showing the max IN packets received in a micro
frame.
42 ; 7. In Bulk Transfer Pipe dropdown menu, select '1: Endpoint 1 IN'. Leave length at 819
2.
43 ; 8. Click BulkTrans. This 64-byte record shows the results of the EP8-IN bulk transfer.
44 ; Each byte is the number of IN packets received by the host in a microframe. '0' a m
icroframe
45 ; with no IN packets.
46 ; NOTE: It's OK to leave the length at 8192 for the 64-byte EP1-IN. Since the default
USB device
47 ; reports EP1 MaxPacketSize=512, a 64 byte packet represents a short packet and termi
nates any IN
48 ; transfer request of under 512 bytes. This saves repeatedly re-typing 64 for EP1 and
8192 for EP8.
A51 MACRO ASSEMBLER BWMETER 06/05/2002 14:07:37 PAGE 2
49 ; 9. An EP1-IN transfer clears the 7-seg readout and resets the analyzer for another try
.
50 ; 10. If at any time, LED4 (D2) lights, the analyzer has incurred wait states (NAK). Debu
g only.
51 ; 11. Same instructions for EP4-OUT [can also use EP2-OUT], except send OUT packets inste
ad of INS.
52 ;
53 ; EP8-IN packs its two buffers with data values 00 and 01; EP6-IN uses EF and FF.
54 ; Note: Hitting the EP1-OUT button (by accident) does not hang the system since this progra
m responds
55 ; to an EP1-OUT request by re-arming the endpoint.
56 ;--------------------------------------------------------------------------
57 $nomod51 ; disable predefined 8051 registers
58 ;--------------------------------------------------------------------------
59 ;$include (fx2regs.inc)
+1 60 ;-----------------------------------------------------------------------------
+1 61 ; File: FX2regs.inc
+1 62 ; Contents: EZ-USB FX2 register declarations and bit mask definitions.
+1 63 ; This file is the equivalent of fx2regs.h but for assembley
code
+1 64 ; Do not modify one without modifying the other.
+1 65 ;
+1 66 ; Copyright (c) 2000 Cypress Semiconductor, All rights reserved
+1 67 ;-----------------------------------------------------------------------------
+1 68
E400 +1 69 GPIF_WAVE_DATA XDATA 0xE400;
E480 +1 70 RES_WAVEDATA_END XDATA 0xE480;
+1 71
+1 72
+1 73
E600 +1 74 CPUCS XDATA 0xE600; // Control & Status
E601 +1 75 IFCONFIG XDATA 0xE601; // Interface Configuration
E602 +1 76 PINFLAGSAB XDATA 0xE602; // FIFO FLAGA and FLAGB Assignments
E603 +1 77 PINFLAGSCD XDATA 0xE603; // FIFO FLAGC and FLAGD Assignments
E604 +1 78 FIFORESET XDATA 0xE604; // Restore FIFOS to default state
E605 +1 79 BREAKPT XDATA 0xE605; // Breakpoint
E606 +1 80 BPADDRH XDATA 0xE606; // Breakpoint Address H
E607 +1 81 BPADDRL XDATA 0xE607; // Breakpoint Address L
E608 +1 82 UART230 XDATA 0xE608; // 230 Kbaud clock for T0,T1,T2
E609 +1 83 FIFOPINPOLAR XDATA 0xE609; // FIFO polarities
E60A +1 84 REVID XDATA 0xE60A; // Chip Revision
+1 85
+1 86
+1 87
E610 +1 88 EP1OUTCFG XDATA 0xE610; // Endpoint 1-OUT Configuration
E611 +1 89 EP1INCFG XDATA 0xE611; // Endpoint 1-IN Configuration
E612 +1 90 EP2CFG XDATA 0xE612; // Endpoint 2 Configuration
E613 +1 91 EP4CFG XDATA 0xE613; // Endpoint 4 Configuration
E614 +1 92 EP6CFG XDATA 0xE614; // Endpoint 6 Configuration
E615 +1 93 EP8CFG XDATA 0xE615; // Endpoint 8 Configuration
E618 +1 94 EP2FIFOCFG XDATA 0xE618; // Endpoint 2 FIFO configuration
E619 +1 95 EP4FIFOCFG XDATA 0xE619; // Endpoint 4 FIFO configuration
E61A +1 96 EP6FIFOCFG XDATA 0xE61A; // Endpoint 6 FIFO configuration
E61B +1 97 EP8FIFOCFG XDATA 0xE61B; // Endpoint 8 FIFO configuration
E620 +1 98 EP2AUTOINLENH XDATA 0xE620; // Endpoint 2 Packet Length H (IN only)
E621 +1 99 EP2AUTOINLENL XDATA 0xE621; // Endpoint 2 Packet Length L (IN only)
E622 +1 100 EP4AUTOINLENH XDATA 0xE622; // Endpoint 4 Packet Length H (IN only)
E623 +1 101 EP4AUTOINLENL XDATA 0xE623; // Endpoint 4 Packet Length L (IN only)
E624 +1 102 EP6AUTOINLENH XDATA 0xE624; // Endpoint 6 Packet Length H (IN only)
E625 +1 103 EP6AUTOINLENL XDATA 0xE625; // Endpoint 6 Packet Length L (IN only)
E626 +1 104 EP8AUTOINLENH XDATA 0xE626; // Endpoint 8 Packet Length H (IN only)
E627 +1 105 EP8AUTOINLENL XDATA 0xE627; // Endpoint 8 Packet Length L (IN only)
E630 +1 106 EP2FIFOPFH XDATA 0xE630; // EP2 Programmable Flag trigger H
E631 +1 107 EP2FIFOPFL XDATA 0xE631; // EP2 Programmable Flag trigger L
E632 +1 108 EP4FIFOPFH XDATA 0xE632; // EP4 Programmable Flag trigger H
E633 +1 109 EP4FIFOPFL XDATA 0xE633; // EP4 Programmable Flag trigger L
A51 MACRO ASSEMBLER BWMETER 06/05/2002 14:07:37 PAGE 3
E634 +1 110 EP6FIFOPFH XDATA 0xE634; // EP6 Programmable Flag trigger H
E635 +1 111 EP6FIFOPFL XDATA 0xE635; // EP6 Programmable Flag trigger L
E636 +1 112 EP8FIFOPFH XDATA 0xE636; // EP8 Programmable Flag trigger H
E637 +1 113 EP8FIFOPFL XDATA 0xE637; // EP8 Programmable Flag trigger L
E640 +1 114 EP2ISOINPKTS XDATA 0xE640; // EP2 (if ISO) IN Packets per frame (1-3)
E641 +1 115 EP4ISOINPKTS XDATA 0xE641; // EP4 (if ISO) IN Packets per frame (1-3)
E642 +1 116 EP6ISOINPKTS XDATA 0xE642; // EP6 (if ISO) IN Packets per frame (1-3)
E643 +1 117 EP8ISOINPKTS XDATA 0xE643; // EP8 (if ISO) IN Packets per frame (1-3)
E648 +1 118 INPKTEND XDATA 0xE648; // Force IN Packet End
+1 119
+1 120
+1 121
E650 +1 122 EP2FIFOIE XDATA 0xE650; // Endpoint 2 Flag Interrupt Enable
E651 +1 123 EP2FIFOIRQ XDATA 0xE651; // Endpoint 2 Flag Interrupt Request
E652 +1 124 EP4FIFOIE XDATA 0xE652; // Endpoint 4 Flag Interrupt Enable
E653 +1 125 EP4FIFOIRQ XDATA 0xE653; // Endpoint 4 Flag Interrupt Request
E654 +1 126 EP6FIFOIE XDATA 0xE654; // Endpoint 6 Flag Interrupt Enable
E655 +1 127 EP6FIFOIRQ XDATA 0xE655; // Endpoint 6 Flag Interrupt Request
E656 +1 128 EP8FIFOIE XDATA 0xE656; // Endpoint 8 Flag Interrupt Enable
E657 +1 129 EP8FIFOIRQ XDATA 0xE657; // Endpoint 8 Flag Interrupt Request
E658 +1 130 IBNIE XDATA 0xE658; // IN-BULK-NAK Interrupt Enable
E659 +1 131 IBNIRQ XDATA 0xE659; // IN-BULK-NAK interrupt Request
E65A +1 132 NAKIE XDATA 0xE65A; // Endpoint Ping NAK interrupt Enable
E65B +1 133 NAKIRQ XDATA 0xE65B; // Endpoint Ping NAK interrupt Request
E65C +1 134 USBIE XDATA 0xE65C; // USB Int Enables
E65D +1 135 USBIRQ XDATA 0xE65D; // USB Interrupt Requests
E65E +1 136 EPIE XDATA 0xE65E; // Endpoint Interrupt Enables
E65F +1 137 EPIRQ XDATA 0xE65F; // Endpoint Interrupt Requests
E660 +1 138 GPIFIE XDATA 0xE660; // GPIF Interrupt Enable
E661 +1 139 GPIFIRQ XDATA 0xE661; // GPIF Interrupt Request
E662 +1 140 USBERRIE XDATA 0xE662; // USB Error Interrupt Enables
E663 +1 141 USBERRIRQ XDATA 0xE663; // USB Error Interrupt Requests
E664 +1 142 ERRCNTLIM XDATA 0xE664; // USB Error counter and limit
E665 +1 143 CLRERRCNT XDATA 0xE665; // Clear Error Counter EC[3..0]
E666 +1 144 INT2IVEC XDATA 0xE666; // Interupt 2 (USB) Autovector
E667 +1 145 INT4IVEC XDATA 0xE667; // Interupt 4 (FIFOS & GPIF) Autovector
E668 +1 146 INTSETUP XDATA 0xE668; // Interrupt 2&4 Setup
+1 147
+1 148
+1 149
E670 +1 150 PORTACFG XDATA 0xE670; // I/O PORTA Alternate Configuration
E671 +1 151 PORTCCFG XDATA 0xE671; // I/O PORTC Alternate Configuration
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -