?? mcbsp.h
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/******************************************************************************/
/* MCBSP.H - TMS320C6x Peripheral Support Library McBSP Support */
/* */
/* This file provides the header for the DSP's McBSP support. */
/* */
/* MACRO FUNCTIONS: */
/* MCBSP_BYTES_PER_WORD() - Return bytes required for word length */
/* MCBSP_ENABLE() - Enables McBSP transit, receive or both */
/* MCBSP_TX_RESET() - Reset McBSP transmitter */
/* MCBSP_RX_RESET() - Reset McBSP receiver */
/* MCBSP_READ() - Read data value from McBSP receive register */
/* MCBSP_WRITE() - Write data value to McBSP transmit register */
/* MCBSP_IO_ENABLE() - Place McBSP in general-purpose I/O mode */
/* MCBSP_IO_DISABLE() - Remove McBSP from general-purpose I/O mode */
/* MCBSP_FRAME_SYNC_ENABLE()- Enables McBSP frame sync generation logic */
/* MCBSP_FRAME_SYNC_RESET() - Resets McBSP frame sync generation logic */
/* MCBSP_SAMPLE_RATE_ENABLE()-Enables McBSP sample rate generator */
/* MCBSP_SAMPLE_RATE_RESET()- Resets McBSP sample rate generator */
/* MCBSP_RRDY() - Returns McBSP receiver ready status */
/* MCBSP_XRDY() - Returns McBSP transmitter ready status */
/* MCBSP_LOOPBACK_ENABLE()- Configures McBSP in digital loopback mode */
/* MCBSP_LOOPBACK_DISABLE()-Disables McBSP digital loopback mode */
/* */
/* FUNCTIONS: */
/* mcbsp_init() - Initializes McBSP registers */
/* */
/* GLOBAL VARIABLES */
/* */
/* REVISION HISTORY: */
/* */
/* DATE DESCRIPTION */
/* ------- -------------------------------------------------------------- */
/* 13JUL98 Changed CLKSTP definition from 10 to 11. */
/* Changed CLKSTP_SZ definition from 3 to 2. */
/* -----> Fixed problem associated with typo in previous */
/* Peripheral Reference Guide */
/* */
/* 15JUN98 Changed McBSP address macros to use "port_no" instead of "port" */
/* parameter for consistency with documentation and other code. */
/* -----> No functional change. */
/* */
/* 11MAY98 Added #define CLK_MODE_CLKS 0x00 */
/* and #define CLK_MODE_CPU 0x01 */
/* -----> Used in programming SRGR */
/* */
/* 11MAY98 Redefined CLKS_POL_FALLING to 0x01 */
/* and CLKS_POL_RISING to 0x00 */
/* -----> Assignments were swapped */
/* */
/* 16JUL98 Added bit definitions for MCCR, RCER and XCER */
/* */
/******************************************************************************/
#ifndef _MCBSP_H_
#define _MCBSP_H_
#ifdef _INLINE
#define __INLINE static inline
#else
#define __INLINE
#endif
/*----------------------------------------------------------------------------*/
/* INCLUDES */
/*----------------------------------------------------------------------------*/
#include "regs.h"
/*----------------------------------------------------------------------------*/
/* DEFINES AND MACROS */
/*----------------------------------------------------------------------------*/
/******************************************************************************/
/****************************** MCSP REGISTERS ********************************/
/* Multi-Channel Buffered Serial Port Control Registers & Bits */
#define MCBSP_ADDR(port_no) (0x018C0000 + ((port_no) * 0x40000))
#define MCBSP_DRR_ADDR(port_no) (MCBSP_ADDR(port_no))
#define MCBSP_DXR_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x04)
#define MCBSP_SPCR_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x08)
#define MCBSP_RCR_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x0c)
#define MCBSP_XCR_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x10)
#define MCBSP_SRGR_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x14)
#define MCBSP_MCR_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x18)
#define MCBSP_RCER_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x1c)
#define MCBSP_XCER_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x20)
#define MCBSP_PCR_ADDR(port_no) ((MCBSP_ADDR(port_no)) + 0x24)
#define MCBSP0_DRR *(volatile unsigned int *)(MCBSP_DRR_ADDR(0))
#define MCBSP0_DXR *(volatile unsigned int *)(MCBSP_DXR_ADDR(0))
#define MCBSP0_SPCR *(volatile unsigned int *)(MCBSP_SPCR_ADDR(0))
#define MCBSP0_RCR *(volatile unsigned int *)(MCBSP_RCR_ADDR(0))
#define MCBSP0_XCR *(volatile unsigned int *)(MCBSP_XCR_ADDR(0))
#define MCBSP0_SRGR *(volatile unsigned int *)(MCBSP_SRGR_ADDR(0))
#define MCBSP0_MCR *(volatile unsigned int *)(MCBSP_MCR_ADDR(0))
#define MCBSP0_RCER *(volatile unsigned int *)(MCBSP_RCER_ADDR(0))
#define MCBSP0_XCER *(volatile unsigned int *)(MCBSP_XCER_ADDR(0))
#define MCBSP0_PCR *(volatile unsigned int *)(MCBSP_PCR_ADDR(0))
#define MCBSP1_DRR *(volatile unsigned int *)(MCBSP_DRR_ADDR(1))
#define MCBSP1_DXR *(volatile unsigned int *)(MCBSP_DXR_ADDR(1))
#define MCBSP1_SPCR *(volatile unsigned int *)(MCBSP_SPCR_ADDR(1))
#define MCBSP1_RCR *(volatile unsigned int *)(MCBSP_RCR_ADDR(1))
#define MCBSP1_XCR *(volatile unsigned int *)(MCBSP_XCR_ADDR(1))
#define MCBSP1_SRGR *(volatile unsigned int *)(MCBSP_SRGR_ADDR(1))
#define MCBSP1_MCR *(volatile unsigned int *)(MCBSP_MCR_ADDR(1))
#define MCBSP1_RCER *(volatile unsigned int *)(MCBSP_RCER_ADDR(1))
#define MCBSP1_XCER *(volatile unsigned int *)(MCBSP_XCER_ADDR(1))
#define MCBSP1_PCR *(volatile unsigned int *)(MCBSP_PCR_ADDR(1))
/* Multi-channel Serial Port Control Register Bits */
#define RRST 0
#define RRDY 1
#define RFULL 2
#define RSYNC_ERR 3
#define RINTM 4
#define RINTM_SZ 2
#define CLKSTP 11
#define CLKSTP_SZ 2
#define RJUST 13
#define RJUST_SZ 2
#define DLB 15
#define XRST 16
#define XRDY 17
#define XEMPTY 18
#define XSYNC_ERR 19
#define XINTM 20
#define XINTM_SZ 2
#define GRST 22
#define FRST 23
/* Multi-channel Serial Port Pin Control Reg Bits */
#define CLKRP 0
#define CLKXP 1
#define FSRP 2
#define FSXP 3
#define DR_STAT 4
#define DX_STAT 5
#define CLKS_STAT 6
#define CLKRM 8
#define CLKXM 9
#define FSRM 10
#define FSXM 11
#define RIOEN 12
#define XIOEN 13
/* Multi-channel Serial Port RX & TX Ctrl Reg Bits */
#define RWDLEN1 5
#define RWDLEN1_SZ 3
#define RFRLEN1 8
#define RFRLEN1_SZ 7
#define RDATDLY 16
#define RDATDLY_SZ 2
#define RFIG 18
#define RCOMPAND 19
#define RCOMPAND_SZ 2
#define RWDLEN2 21
#define RWDLEN2_SZ 3
#define RFRLEN2 24
#define RFRLEN2_SZ 7
#define RPHASE 31
#define XWDLEN1 5
#define XWDLEN1_SZ 3
#define XFRLEN1 8
#define XFRLEN1_SZ 7
#define XDATDLY 16
#define XDATDLY_SZ 2
#define XFIG 18
#define XCOMPAND 19
#define XCOMPAND_SZ 2
#define XWDLEN2 21
#define XWDLEN2_SZ 3
#define XFRLEN2 24
#define XFRLEN2_SZ 7
#define XPHASE 31
/* Multi-channel Serial Port Sample Rate Gen Reg Bits */
#define CLKGDV 0
#define CLKGDV_SZ 8
#define FWID 8
#define FWID_SZ 8
#define FPER 16
#define FPER_SZ 12
#define FSGM 28
#define CLKSM 29
#define CLKSP 30
#define GSYNC 31
/* Multi-channel Serial Port Multi-Chan Ctrl Reg Bits */
#define RMCM 0
#define RCBLK 2
#define RCBLK_SZ 3
#define RPABLK 5
#define RPABLK_SZ 2
#define RPBBLK 7
#define RPBBLK_SZ 2
#define XMCM 16
#define XMCM_SZ 2
#define XCBLK 18
#define XCBLK_SZ 3
#define XPABLK 21
#define XPABLK_SZ 2
#define XPBBLK 23
#define XPBBLK_SZ 2
/* Multi-channel Serial Port Rec Enable Register Bits */
#define RCEA0 0
#define RCEA1 1
#define RCEA2 2
#define RCEA3 3
#define RCEA4 4
#define RCEA5 5
#define RCEA6 6
#define RCEA7 7
#define RCEA8 8
#define RCEA9 9
#define RCEA10 10
#define RCEA11 11
#define RCEA12 12
#define RCEA13 13
#define RCEA14 14
#define RCEA15 15
#define RCEB0 16
#define RCEB1 17
#define RCEB2 18
#define RCEB3 19
#define RCEB4 20
#define RCEB5 21
#define RCEB6 22
#define RCEB7 23
#define RCEB8 24
#define RCEB9 25
#define RCEB10 26
#define RCEB11 27
#define RCEB12 28
#define RCEB13 29
#define RCEB14 30
#define RCEB15 31
/* Multi-channel Serial Port TX Enable Register Bits */
#define XCEA0 0
#define XCEA1 1
#define XCEA2 2
#define XCEA3 3
#define XCEA4 4
#define XCEA5 5
#define XCEA6 6
#define XCEA7 7
#define XCEA8 8
#define XCEA9 9
#define XCEA10 10
#define XCEA11 11
#define XCEA12 12
#define XCEA13 13
#define XCEA14 14
#define XCEA15 15
#define XCEB0 16
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