mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);        FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);        FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);        FP_MUL_D(DR, DA, DB);        FP_ADD_D(DR, DR, DC);	FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);        return _fex;}/* Multiply and add double */static int emu_madb (struct pt_regs *regs, int rx, double *val, int rz) {        FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DC); FP_DECL_D(DR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);        FP_UNPACK_DP(DB, val);        FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);        FP_MUL_D(DR, DA, DB);        FP_ADD_D(DR, DR, DC);	FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);        return _fex;}/* Multiply and add float */static int emu_maebr (struct pt_regs *regs, int rx, int ry, int rz) {        FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);        FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);        FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);        FP_MUL_S(SR, SA, SB);        FP_ADD_S(SR, SR, SC);	FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);        return _fex;}/* Multiply and add float */static int emu_maeb (struct pt_regs *regs, int rx, float *val, int rz) {        FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);        FP_UNPACK_SP(SB, val);        FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);        FP_MUL_S(SR, SA, SB);        FP_ADD_S(SR, SR, SC);	FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);        return _fex;}/* Multiply and subtract double */static int emu_msdbr (struct pt_regs *regs, int rx, int ry, int rz) {        FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DC); FP_DECL_D(DR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);        FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);        FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);        FP_MUL_D(DR, DA, DB);        FP_SUB_D(DR, DR, DC);	FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);        return _fex;}/* Multiply and subtract double */static int emu_msdb (struct pt_regs *regs, int rx, double *val, int rz) {        FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DC); FP_DECL_D(DR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);        FP_UNPACK_DP(DB, val);        FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);        FP_MUL_D(DR, DA, DB);        FP_SUB_D(DR, DR, DC);	FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);        return _fex;}/* Multiply and subtract float */static int emu_msebr (struct pt_regs *regs, int rx, int ry, int rz) {        FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);        FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);        FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);        FP_MUL_S(SR, SA, SB);        FP_SUB_S(SR, SR, SC);	FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);        return _fex;}/* Multiply and subtract float */static int emu_mseb (struct pt_regs *regs, int rx, float *val, int rz) {        FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);        FP_UNPACK_SP(SB, val);        FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);        FP_MUL_S(SR, SA, SB);        FP_SUB_S(SR, SR, SC);	FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);        return _fex;}/* Set floating point control word */static int emu_sfpc (struct pt_regs *regs, int rx, int ry) {        __u32 temp;        temp = regs->gprs[rx];        if ((temp & ~FPC_VALID_MASK) != 0)		return SIGILL;	current->thread.fp_regs.fpc = temp;        return 0;}/* Square root long double */static int emu_sqxbr (struct pt_regs *regs, int rx, int ry) {        FP_DECL_Q(QA); FP_DECL_Q(QR);        FP_DECL_EX;	mathemu_ldcv cvt;        int mode;	mode = current->thread.fp_regs.fpc & 3;        cvt.w.high = current->thread.fp_regs.fprs[ry].ui;        cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;        FP_UNPACK_QP(QA, &cvt.ld);	FP_SQRT_Q(QR, QA);        FP_PACK_QP(&cvt.ld, QR);        current->thread.fp_regs.fprs[rx].ui = cvt.w.high;        current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;        emu_set_CC_cs(regs, QR_c, QR_s);        return _fex;}/* Square root double */static int emu_sqdbr (struct pt_regs *regs, int rx, int ry) {        FP_DECL_D(DA); FP_DECL_D(DR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);	FP_SQRT_D(DR, DA);	FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);        emu_set_CC_cs(regs, DR_c, DR_s);        return _fex;}/* Square root double */static int emu_sqdb (struct pt_regs *regs, int rx, double *val) {        FP_DECL_D(DA); FP_DECL_D(DR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, val);	FP_SQRT_D(DR, DA);	FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);        emu_set_CC_cs(regs, DR_c, DR_s);        return _fex;}/* Square root float */static int emu_sqebr (struct pt_regs *regs, int rx, int ry) {        FP_DECL_S(SA); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);	FP_SQRT_S(SR, SA);	FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);        emu_set_CC_cs(regs, SR_c, SR_s);        return _fex;}/* Square root float */static int emu_sqeb (struct pt_regs *regs, int rx, float *val) {        FP_DECL_S(SA); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, val);	FP_SQRT_S(SR, SA);	FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);        emu_set_CC_cs(regs, SR_c, SR_s);        return _fex;}/* Subtract long double */static int emu_sxbr (struct pt_regs *regs, int rx, int ry) {        FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);        FP_DECL_EX;	mathemu_ldcv cvt;        int mode;	mode = current->thread.fp_regs.fpc & 3;        cvt.w.high = current->thread.fp_regs.fprs[rx].ui;        cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;        FP_UNPACK_QP(QA, &cvt.ld);        cvt.w.high = current->thread.fp_regs.fprs[ry].ui;        cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;        FP_UNPACK_QP(QB, &cvt.ld);        FP_SUB_Q(QR, QA, QB);        FP_PACK_QP(&cvt.ld, QR);        current->thread.fp_regs.fprs[rx].ui = cvt.w.high;        current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;        emu_set_CC_cs(regs, QR_c, QR_s);        return _fex;}/* Subtract double */static int emu_sdbr (struct pt_regs *regs, int rx, int ry) {        FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);        FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);        FP_SUB_D(DR, DA, DB);	FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);        emu_set_CC_cs(regs, DR_c, DR_s);        return _fex;}/* Subtract double */static int emu_sdb (struct pt_regs *regs, int rx, double *val) {        FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);        FP_UNPACK_DP(DB, val);        FP_SUB_D(DR, DA, DB);	FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);        emu_set_CC_cs(regs, DR_c, DR_s);        return _fex;}/* Subtract float */static int emu_sebr (struct pt_regs *regs, int rx, int ry) {        FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);        FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);        FP_SUB_S(SR, SA, SB);	FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);        emu_set_CC_cs(regs, SR_c, SR_s);        return _fex;}/* Subtract float */static int emu_seb (struct pt_regs *regs, int rx, float *val) {        FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);        FP_DECL_EX;        int mode;	mode = current->thread.fp_regs.fpc & 3;        FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);        FP_UNPACK_SP(SB, val);        FP_SUB_S(SR, SA, SB);	FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);        emu_set_CC_cs(regs, SR_c, SR_s);        return _fex;}/* Test data class long double */static int emu_tcxb (struct pt_regs *regs, int rx, long val) {        FP_DECL_Q(QA);	mathemu_ldcv cvt;	int bit;        cvt.w.high = current->thread.fp_regs.fprs[rx].ui;        cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;        FP_UNPACK_RAW_QP(QA, &cvt.ld);	switch (QA_e) {	default:		bit = 8;		/* normalized number */		break;	case 0:		if (_FP_FRAC_ZEROP_4(QA))			bit = 10;	/* zero */		else			bit = 6;	/* denormalized number */		break;	case _FP_EXPMAX_Q:		if (_FP_FRAC_ZEROP_4(QA))			bit = 4;	/* infinity */		else if (_FP_FRAC_HIGH_RAW_Q(QA) & _FP_QNANBIT_Q)			bit = 2;	/* quiet NAN */		else			bit = 0;	/* signaling NAN */		break;	}	if (!QA_s)		bit++;	emu_set_CC(regs, ((__u32) val >> bit) & 1);        return 0;}/* Test data class double */static int emu_tcdb (struct pt_regs *regs, int rx, long val) {        FP_DECL_D(DA);	int bit;        FP_UNPACK_RAW_DP(DA, &current->thread.fp_regs.fprs[rx].d);	switch (DA_e) {	default:		bit = 8;		/* normalized number */		break;	case 0:		if (_FP_FRAC_ZEROP_2(DA))			bit = 10;	/* zero */		else			bit = 6;	/* denormalized number */		break;	case _FP_EXPMAX_D:		if (_FP_FRAC_ZEROP_2(DA))			bit = 4;	/* infinity */		else if (_FP_FRAC_HIGH_RAW_D(DA) & _FP_QNANBIT_D)			bit = 2;	/* quiet NAN */		else			bit = 0;	/* signaling NAN */		break;	}	if (!DA_s)		bit++;	emu_set_CC(regs, ((__u32) val >> bit) & 1);        return 0;}/* Test data class float */static int emu_tceb (struct pt_regs *regs, int rx, long val) {        FP_DECL_S(SA);	int bit;        FP_UNPACK_RAW_SP(SA, &current->thread.fp_regs.fprs[rx].f);	switch (SA_e) {	default:		bit = 8;		/* normalized number */		break;	case 0:		if (_FP_FRAC_ZEROP_1(SA))			bit = 10;	/* zero */		else			bit = 6;	/* denormalized number */		break;	case _FP_EXPMAX_S:		if (_FP_FRAC_ZEROP_1(SA))			bit = 4;	/* infinity */		else if (_FP_FRAC_HIGH_RAW_S(SA) & _FP_QNANBIT_S)			bit = 2;	/* quiet NAN */		else			bit = 0;	/* signaling NAN */		break;	}	if (!SA_s)		bit++;	emu_set_CC(regs, ((__u32) val >> bit) & 1);        return 0;}static inline void emu_load_regd(int reg) {        if ((reg&9) != 0)         /* test if reg in {0,2,4,6} */                return;        asm volatile (            /* load reg from fp_regs.fprs[reg] */                "     bras  1,0f\n"                "     ld    0,0(%1)\n"