/* * v320usc.h: Register defines for the V320USC family of devices. * * Copyright (C) 1999,2000 Dan Aizenstros (dan@vcubed.com) * * $Id: pci-v320usc.h,v 1.1 2003/02/20 04:26:36 gerg Exp $ */#ifndef _V320USC_H_#define _V320USC_H_#include <linux/pci.h>/* * General parameters *//* set debug level 4=verbose...1=terse */#define DEBUG_PCI 3// #undef DEBUG_PCI#ifdef DEBUG_PCI#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }#else#define PCIDBG(n, x...)#endif#if 0/* startup values */#define PCI_PROBE_BIOS 1#define PCI_PROBE_CONF1 2#define PCI_PROBE_CONF2 4#define PCI_NO_SORT 0x100#define PCI_BIOS_SORT 0x200#define PCI_NO_CHECKS 0x400#define PCI_ASSIGN_ROMS 0x1000#define PCI_BIOS_IRQ_SCAN 0x2000#endif/* *	platform specific parameters */ /* * PCI Command Register * - Offset 04h, Size 16 bits */#define PCI_CMD_W_IO_EN			0x0001		/* I/O access */#define PCI_CMD_W_MEM_EN		0x0002		/* Memory access */#define PCI_CMD_W_MASTER_EN		0x0004		/* PCI Master */#define PCI_CMD_W_MWI_EN		0x0010		/* Memory Write and */							/* Invalidate enable            */#define PCI_CMD_W_PAR_EN		0x0040		/* Parity error */#define PCI_CMD_W_SERR_EN		0x0100		/* System error */							/* If PAR_EN is enabled then SERR is  */							/* driven in response to parity error */#define PCI_CMD_W_FBB_EN		0x0200		/* Fast back to back */							/* transfers when Bus Master     *//* * PCI Status Register * - Offset 06h, Size 16 bits */#define PCI_STAT_W_NEW_CAP		0x0010		/* New Capabilites          */#define PCI_STAT_W_UDF			0x0040		/* User Defined Feature     */#define PCI_STAT_W_FAST_BACK		0x0008		/* Fast Back to Back Target */							/* - Used to indicate ability of this   */							/* device to other Bus Masters          */#define PCI_STAT_W_PAR_REP		0x0010		/* Data Parity Report when    */							/* USC is a Bus Master and PERR is driven */#define PCI_STAT_W_DEVSEL_MASK		0x0600		/* 10-9 Bits Device Select */							/* Timing                              */#define PCI_STAT_W_DEVSEL_SHIFT		9#define PCI_STAT_W_T_ABORT		0x1000		/* Target Abort - set in */							/* response to a target abort detected */							/* while USC was a Bus Master          */#define PCI_STAT_W_M_ABORT		0x2000		/* Master Abort - set in   */							/* response to a master abort detected */							/* while USC was a Bus Master          */#define PCI_STAT_W_SYS_ERR		0x4000		/* System Error - set in */							/* response to a system error on the */							/* SERR pin                          */#define PCI_STAT_W_PAR_ERR		0x8000		/* Parity Error - set in */							/* response to a parity error on the */							/* PCI bus                           *//* * PCI Class and Revision Register * - Offset 08h, Size 32 bits */#define PCI_CC_REV_VREV_MASK		0x0000000f	/* 3-0 Bits Stepping ID  */							/* Rev A = 0,Rev B0 = 1, Rev B1 = 2, */							/* Rev B2 = 3 */#define PCI_CC_REV_VREV_SHIFT		0#define PCI_CC_REV_UREV_MASK		0x000000f0	/* 7-4 Bits User Revision ID */							/* user definable for system revisions   */#define PCI_CC_REV_UREV_SHIFT		4#define PCI_CC_REV_PROG_IF_MASK		0x0000ff00	/* 15-8 Bits PCI Programming */							/* Interface code                        */#define PCI_CC_REV_PROG_IF_SHIFT	8#define PCI_CC_REV_SUB_CLASS_MASK	0x00ff0000	/* 23-16 Bits PCI Sub Class */#define PCI_CC_REV_SUB_CLASS_SHIFT	16#define PCI_CC_REV_BASE_CLASS_MASK	0xff000000	/* 32-24 Bits PCI Base Class */#define PCI_CC_REV_BASE_CLASS_SHIFT 	24/* * PCI Access to local memory map access * - Offset 10h, Size 32 bits (I2O mode) */#define PCI_I2O_BASE_IO			0x00000001	/* I/O 1 - I/O space */							/* 0 - Memory Space              */#define PCI_I2O_BASE_TYPE_MASK		0x00000006	/* 2-1 Bits Address range */							/* type                               */#define PCI_I2O_BASE_TYPE_SHIFT		1		/* 0 - device can be mapped */							/* any where in a 32 bit address space  */#define PCI_I2O_BASE_PREFETCH		0x00000008	/* Prefetchable - no effect */#define PCI_I2O_BASE_ADR_BASE_MASK	0xfff00000	/* 31-20 Bits Base address */							/* of ATU                              */#define PCI_I2O_BASE_ADR_BASE_SHIFT	20/* * PCI Access to local memory map access * - Offset 14h, Size 32 bits */#define PCI_MEM_BASE_IO			0x00000001	/* I/O 1 - I/O space */							/* 0 - Memory Space              */#define PCI_MEM_BASE_TYPE_MASK		0x00000006	/* 2-1 Bits Address range */							/* type                               */#define PCI_MEM_BASE_TYPE_SHIFT		1		/* 0 - device can be mapped */							/* any where in a 32 bit address space  */#define PCI_MEM_BASE_PREFETCH		0x00000008	/* Prefetchable - no effect */#define PCI_MEM_BASE_ADR_BASE_MASK	0xfff00000	/* 31-20 Bits Base address */							/* of ATU                              */#define PCI_MEM_BASE_ADR_BASE_SHIFT	20/* * PCI Bus Parameters Register * - Offset 3ch, Size 32 bits */#define PCI_BPARAM_INT_LINE_MASK	0x000000ff	/* 7-0 Bits Interrupt Line */#define PCI_BPARAM_INT_LINE_SHIFT	0#define PCI_BPARAM_INT_PIN_MASK		0x00000700	/* 10-8 Bits Interrupt Pin */							/* 0 - disable, 1 - INTA, 2 - INT B    */							/* 3 - INT C, 4 - INT C                */#define PCI_BPARAM_INT_PIN_SHIFT	8#define PCI_BPARAM_MIN_GRANT_MASK	0x00ff0000	/* 23-16 Bits Minimum Grant */#define PCI_BPARAM_MIN_GRANT_SHIFT	16#define PCI_BPARAM_MAX_LAT_MASK		0xff000000	/* 31-24 Bits Maximum Latency */#define PCI_BPARAM_MAX_LAT_SHIFT	24/* * LB_PCI_BASEx Registers * - Offset 60h, Size 32 bits * - Offset 64h, Size 32 bits */#define LB_PCI_BASEX_ALOW_MASK		0x00000003	/* select value AD1:0 */#define LB_PCI_BASEX_ALOW_SHIFT		0x00000000#define LB_PCI_BASEX_ERR_EN		0x00000004#define LB_PCI_BASEX_PREFETCH		0x00000008	/* prefetch */#define LB_PCI_BASEX_SIZE_DISABLE	0x00000000#define LB_PCI_BASEX_SIZE_16MB		0x00000010#define LB_PCI_BASEX_SIZE_32MB		0x00000020#define LB_PCI_BASEX_SIZE_64MB		0x00000030#define LB_PCI_BASEX_SIZE_128MB		0x00000040#define LB_PCI_BASEX_SIZE_256MB		0x00000050#define LB_PCI_BASEX_SIZE_512MB		0x00000060#define LB_PCI_BASEX_SIZE_1GB		0x00000070#define LB_PCI_BASEX_BYTE_SWAP_NO	0x00000000	/* No swap 32 bits */#define LB_PCI_BASEX_BYTE_SWAP_16	0x00000100	/* 16 bits */#define LB_PCI_BASEX_BYTE_SWAP_8	0x00000200	/* bits */#define LB_PCI_BASEX_BYTE_SWAP_AUTO	0x00000300	/* Auto swap use BE[3:0] */#define LB_PCI_BASEX_COMBINE		0x00000800	/* Burst Write Combine */#define LB_PCI_BASEX_PCI_CMD_MASK	0x0000e000#define LB_PCI_BASEX_PCI_CMD_SHIFT	13#define LB_PCI_BASEX_INT_ACK		0x00000000	/* Interrupt Ack */#define LB_PCI_BASEX_IO			0x00002000	/* I/O Read/Write */#define LB_PCI_BASEX_MEMORY		0x00006000	/* Memory Read/Write */#define LB_PCI_BASEX_CONFIG		0x0000a000	/* Configuration Read/Write */#define LB_PCI_BASEX_MULTI_MEMORY	0x0000c000	/* Multiple Memory Read/Write */#define LB_PCI_BASEX_MEMORY_INVALIDATE	0x0000e000	/* Multiple Memory Read/e */							/* Write Invalidate       */#define LB_PCI_BASEX_MAP_ADR_MASK	0x00ff0000	/* PCI Address map */#define LB_PCI_BASEX_MAP_ADR_SHIFT	16#define LB_PCI_BASEX_BASE		0xff000000	/* Local Address base */#define LB_PCI_BASEX_BASE_ADR_SHIFT	24/* * SDRAM Local Base Address Register  * - Offset 78h, Size 32 bits */#define LB_SDRAM_BASE_ENABLE		0x01		/* must be enabled to access */#define LB_SDRAM_BASE_SIZE_64M		0x00#define LB_SDRAM_BASE_SIZE_128M		0x10#define LB_SDRAM_BASE_SIZE_256M		0x20#define LB_SDRAM_BASE_SIZE_512M		0x30#define LB_SDRAM_BASE_SIZE_1G		0x40#define LB_SDRAM_BASE_MASK		0xfc000000#define LB_SDRAM_BASE_SHIFT		26/* * Interrupt Configuration Register * - Offset e0h, Size 32 bits * - Offset e4h, Size 32 bits * - Offset e8h, Size 32 bits * - Offset 158h, Size 32 bits */#define INT_CFGX_LB_MBI			0x00000001#define INT_CFGX_PCI_MBI		0x00000002#define INT_CFGX_I2O_OP_NE		0x00000008#define INT_CFGX_I2O_IF_NF		0x00000010#define INT_CFGX_I2O_IP_NE		0x00000020#define INT_CFGX_I2O_OP_NF		0x00000040#define INT_CFGX_I2O_OF_NE		0x00000080#define INT_CFGX_INT0			0x00000100#define INT_CFGX_INT1			0x00000200#define INT_CFGX_INT2			0x00000400#define INT_CFGX_INT3			0x00000800#define INT_CFGX_TIMER0			0x00001000#define INT_CFGX_TIMER1			0x00002000