/* *	Low-Level PCI Access for i386 machines. * *	(c) 1999 Martin Mares <mj@ucw.cz> */#undef DEBUG#ifdef DEBUG#define DBG(x...) printk(x)#else#define DBG(x...)#endif#define PCI_PROBE_BIOS		0x0001#define PCI_PROBE_CONF1		0x0002#define PCI_PROBE_CONF2		0x0004#define PCI_NO_SORT		0x0100#define PCI_BIOS_SORT		0x0200#define PCI_NO_CHECKS		0x0400#define PCI_ASSIGN_ROMS		0x1000#define PCI_BIOS_IRQ_SCAN	0x2000#define PCI_ASSIGN_ALL_BUSSES	0x4000extern unsigned int pci_probe;/* pci-i386.c */extern unsigned int pcibios_max_latency;extern u8 pci_cache_line_size;void pcibios_resource_survey(void);void pcibios_set_cacheline_size(void);int pcibios_enable_resources(struct pci_dev *, int mask);/* pci-pc.c */extern int pcibios_last_bus;extern struct pci_bus *pci_root_bus;extern struct pci_ops *pci_root_ops;struct irq_routing_table *pcibios_get_irq_routing_table(void);int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);/* pci-irq.c */struct irq_info {	u8 bus, devfn;			/* Bus, device and function */	struct {		u8 link;		/* IRQ line ID, chipset dependent, 0=not routed */		u16 bitmap;		/* Available IRQs */	} __attribute__((packed)) irq[4];	u8 slot;			/* Slot number, 0=onboard */	u8 rfu;} __attribute__((packed));struct irq_routing_table {	u32 signature;			/* PIRQ_SIGNATURE should be here */	u16 version;			/* PIRQ_VERSION */	u16 size;			/* Table size in bytes */	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */	u16 exclusive_irqs;		/* IRQs devoted exclusively to PCI usage */	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of interrupt router */	u32 miniport_data;		/* Crap */	u8 rfu[11];	u8 checksum;			/* Modulo 256 checksum must give zero */	struct irq_info slots[0];} __attribute__((packed));extern unsigned int pcibios_irq_mask;void pcibios_irq_init(void);void pcibios_fixup_irqs(void);void pcibios_enable_irq(struct pci_dev *dev);void pci_iommu_init(void);