# AP.BCD file. This file contains the board definition for the
# ARM Integrator AP platform.
#
# Copyright 2001-2003 ARM Limited.
[BOARD=AP] 
Advanced_Information.ARM={\
  Memory_block.M_AP_BOOTROM={\
    start=0x20000000:length=0x80000:access=ROM:description="Boot"\
  }:Memory_block.M_FLASH={\
    start=0x24000000:length=0x2000000:access=Flash:\
        flash_type="$RVDEBUG_BASE/flash/examples/IntegratorAP/flash_IntegratorAP.fme":\
        description="Intel"\
  }:Memory_block.M_AP_SSRAM={\
    start=0x28000000:length=0x80000:description="AP SSRAM"\
  }:Memory_block.M_CS3={\
    start=0x2C000000:length=0x4000000:access=NOMEM\
  }:Memory_block.M_AP_REGS={\
    start=0x11000000:length=0xF000000:description="AP Registers"\
  }:Memory_block.M_PCI={\
    start=0x40000000:length=0x40000000\
  }:Memory_block.M_CM0={\
    start=0x80000000:length=0x10000000:wait_states=2\
  }:Memory_block.M_CM1={\
    start=0x90000000:length=0x10000000:wait_states=2\
  }:Memory_block.M_CM2={\
    start=0xA0000000:length=0x10000000:wait_states=2\
  }:Memory_block.M_CM3={\
    start=0xB0000000:length=0x10000000:wait_states=2\
  }:Map_rule.R_CM0={\
    register=G_SC_DEC:mask=0x0001:value=0x0001:on_equal=M_CM0\
  }:Map_rule.R_CM1={\
    register=G_SC_DEC:mask=0x0002:value=0x0002:on_equal=M_CM1\
  }:Map_rule.R_CM2={\
    register=G_SC_DEC:mask=0x0004:value=0x0004:on_equal=M_CM2\
  }:Map_rule.R_CM3={\
    register=G_SC_DEC:mask=0x0008:value=0x0008:on_equal=M_CM3\
  }:Map_rule.R_PCI={\
    register=G_SC_PCI:mask=0x0002:value=0x0002:on_equal=M_PCI\
  }:Register_enum.E_MEMSIZE={\
    names="8,16,32,rsvd"\
  }:Register_enum.E_WREN={\
    names="DISABLED,ENABLED"\
  }:Register_enum.E_SSRAM={\
    names="ASYNC,SYNC"\
  }:Register_enum.E_WAIT={\
    names="2,3,4,5,6,7,8,9,10,11,12,13,14,15,15,16"\
  }:Register_enum.E_ENABLE={\
    names="DISABLED,ENABLED"\
  }:Register_enum.E_TMODE={\
    names="free,periodic"\
  }:Register_enum.E_TPRESCALE={\
    names="none,div16,div256,undef."\
  }:Register_enum.E_LSTAT={\
    names="idle,busy"\
  }:Register_enum.E_LONOFF={\
    names="OFF,ON"\
  }:Register_enum.E_ENABLE={\
    names="DISABLED,ENABLED"\
  }:Register_enum.E_UPARITY={\
    names="ODD,EVEN"\
  }:Register_enum.E_WORDLEN={\
    names="5,6,7,8"\
  }:Register_enum.E_KFORCE={\
    names="...,LOW"\
  }:Register_enum.E_KTYPE={\
    names="PS2/AT,no line ctrl"\
  }:Register_enum.E_BUSY={\
    names="IDLE,BUSY"\
  }:Register_enum.E_EMPTY={\
    names="...,EMPTY"\
  }:Register_enum.E_FULL={\
    names="...,FULL"\
  }:Register_enum.E_ERROR={\
    names="OK,ERROR"\
  }:Register_enum.E_STP2_1={\
    names="1-bit,2-bits"\
  }:Register_enum.E_BUSY={\
    names="Ready,Busy"\
  }:Register_enum.E_INT={\
    names="...,INT"\
  }:Register_enum.E_SET={\
    names="...,Set"\
  }:Register_enum.E_CLR={\
    names="...,CLR"\
  }:Register_enum.E_ONEBIT={\
    names="0,1"\
  }:Register_enum.E_PRESENT={\
    names="...,Avail."\
  }:Register.default={\
    bit_fields.default={}\
  }:Concat_Register.default={}:Peripherals.SYSCTRL={\
    Register.G_SC_ID={\
      start=0x11000000:length=4:read_only=True:bit_fields.B_REV_AP={\
        size=4:gui_name="Rev."\
      }:bit_fields.B_BUILD_AP={\
        position=4:size=8:gui_name="Build"\
      }:bit_fields.B_FPGA_AP={\
        position=12:size=4:gui_name="FPGA"\
      }:bit_fields.B_ARCH_AP={\
        position=16:size=8:gui_name="Arch."\
      }:bit_fields.B_MAN_AP={\
        position=24:size=8:gui_name="Man."\
      }\
    }:Register.G_SC_SC={\
      start=0x11000004:length=2:bit_fields.B_S_VDW={\
        size=8:gui_name="VDW"\
      }:bit_fields.B_DIVX_Y={\
        position=8:gui_name="DIVX_Y"\
      }\
    }:Register.G_SC_CTRLS={\
      start=0x11000008:bit_fields.B_SOFTRST_S={\
        enum=E_SET:gui_name="SoftResetS"\
      }:bit_fields.B_FLASHVPP_S={\
        position=1:enum=E_SET:gui_name="FlashVPPS"\
      }:bit_fields.B_FLASHWP_S={\
        position=2:enum=E_SET:gui_name="FlashWPS"\
      }:bit_fields.B_UART1DTR_S={\
        position=4:enum=E_SET:gui_name="UDTR1S"\
      }:bit_fields.B_UART1RTS_S={\
        position=5:enum=E_SET:gui_name="URTS1S"\
      }:bit_fields.B_UART0DTR_S={\
        position=6:enum=E_SET:gui_name="UDTR0S"\
      }:bit_fields.B_UART0RTS_S={\
        position=7:enum=E_SET:gui_name="URTS0S"\
      }\
    }:Register.G_SC_CTRLC={\
      start=0x1100000C:volatile=on_write:bit_fields.B_SOFTRST_C={\
        enum=E_CLR:gui_name="SoftResetC"\
      }:bit_fields.B_FLASHVPP_C={\
        position=1:enum=E_CLR:gui_name="FlashVPPC"\
      }:bit_fields.B_FLASHWP_C={\
        position=2:enum=E_CLR:gui_name="FlashWPC"\
      }:bit_fields.B_UART1DTR_C={\
        position=4:enum=E_CLR:gui_name="UDTR1C"\
      }:bit_fields.B_UART1RTS_C={\
        position=5:enum=E_CLR:gui_name="URTS1C"\
      }:bit_fields.B_UART0DTR_C={\
        position=6:enum=E_CLR:gui_name="UDTR0C"\
      }:bit_fields.B_UART0RTS_C={\
        position=7:enum=E_CLR:gui_name="URTS0C"\
      }\
    }:Register.G_SC_DEC={\
      start=0x11000010:bit_fields.B_PPRES={\
        size=4:read_only=True:gui_name="PPRES"\
      }:bit_fields.B_EPRES={\
        position=4:size=4:read_only=True:gui_name="EPRES"\
      }:bit_fields.B_PPRES0={\
        enum=E_PRESENT:gui_name="HDR0"\
      }:bit_fields.B_PPRES1={\
        position=1:enum=E_PRESENT:gui_name="HDR1"\
      }:bit_fields.B_PPRES2={\
        position=2:enum=E_PRESENT:gui_name="HDR2"\
      }:bit_fields.B_PPRES3={\
        position=3:enum=E_PRESENT:gui_name="HDR3"\
      }:bit_fields.B_EPRES0={\
        position=4:enum=E_PRESENT:gui_name="EXP0"\
      }:bit_fields.B_EPRES1={\
        position=5:enum=E_PRESENT:gui_name="EXP1"\
      }:bit_fields.B_EPRES2={\
        position=6:enum=E_PRESENT:gui_name="EXP2"\
      }:bit_fields.B_EPRES3={\
        position=7:enum=E_PRESENT:gui_name="EXP3"\
      }\
    }:Register.G_SC_ARB={\
      start=0x11000014:length=4:bit_fields.B_TCOUNT={\
        size=5:gui_name="TCOUNT"\
      }:bit_fields.B_CCOUNT={\
        position=8:size=12:gui_name="CCOUNT"\
      }\
    }:Register.G_SC_PCI={\
      start=0x11000018:length=4:bit_fields.B_PCIEN={\
        position=0:enum=E_ENABLE:read_only=False:gui_name="PCI"\
      }:bit_fields.B_PCIINT_CLR={\
        position=1:enum=E_CLR:gui_name="PCIINT"\
      }\
    }:Register.G_SC_LOCK={\
      start=0x1100001C:length=4:bit_fields.B_LOCKVAL={\
        size=16:gui_name="Key"\
      }:bit_fields.B_LOCKED={\
        position=16:enum=E_ENABLE:read_only=True:gui_name="Lock"\
      }\
    }:Register.G_SC_LBFADDR={\
      start=0x11000020:length=4:gui_name="PCI Fault Addr.":bit_fields.default={}\
    }:Register.G_SC_LBFCODE={\
      start=0x11000024:read_only=True:gui_name="PCI Fault Code":bit_fields.B_RLBFINT={\
        enum=E_INT:read_only=True:gui_name="Fault"\
      }:bit_fields.B_MASTER={\
        position=1:enum=E_ONEBIT:gui_name="Master"\
      }:bit_fields.B_LREAD={\
        position=2:enum=E_ONEBIT:gui_name="LRead"\
      }:bit_fields.B_LBURST={\
        position=3:enum=E_ONEBIT:gui_name="LBurst"\
      }:bit_fields.B_BEN0={\
        position=4:enum=E_ONEBIT:gui_name="Byte0"\
      }:bit_fields.B_BEN1={\
        position=5:enum=E_ONEBIT:gui_name="Byte1"\
      }:bit_fields.B_BEN2={\
        position=6:enum=E_ONEBIT:gui_name="Byte2"\
      }:bit_fields.B_BEN3={\
        position=7:enum=E_ONEBIT:gui_name="Byte3"\
      }\
    }:Register.G_SC_FLAGSSET={\
      start=0x11000030:length=4:gui_name="FlagS":bit_fields.default={}\
    }:Register.G_SC_FLAGSCLR={\
      start=0x11000034:length=4:gui_name="FlagC":bit_fields.default={}\
    }:Register.G_SC_NVFLAGSSET={\
      start=0x11000038:length=4:gui_name="NVFlagS":bit_fields.default={}\
    }:Register.G_SC_NVFLAGSCLR={\
      start=0x1100003C:length=4:gui_name="NVFlagC":bit_fields.default={}\
    }\
  }:Peripherals.EBI={\
    Register.G_EBI_CSR0={\
      start=0x12000000:length=4:gui_name="CSR0":bit_fields.B_MEMSIZE0={\
        size=2:enum=E_MEMSIZE:gui_name="Size0"\
      }:bit_fields.B_WREN0={\
        position=2:size=1:enum=E_WREN:gui_name="WREN0"\
      }:bit_fields.B_SSRAM0={\
        position=3:enum=E_SSRAM:gui_name="Type"\
      }:bit_fields.B_WAIT0={\
        position=4:size=4:enum=E_WAIT:gui_name="Wait0"\
      }\
    }:Register.G_EBI_CSR1={\
      start=0x12000004:length=4:gui_name="CSR1":bit_fields.B_MEMSIZE1={\
        size=2:enum=E_MEMSIZE:gui_name="Size1"\
      }:bit_fields.B_WREN1={\
        position=2:size=1:enum=E_WREN:gui_name="WREN1"\
      }:bit_fields.B_SSRAM1={\
        position=3:enum=E_SSRAM:gui_name="Type1"\
      }:bit_fields.B_WAIT1={\
        position=4:size=4:enum=E_WAIT:gui_name="Wait1"\
      }\
    }:Register.G_EBI_CSR2={\
      start=0x12000008:length=4:gui_name="CSR2":bit_fields.B_MEMSIZE2={\
        size=2:enum=E_MEMSIZE:gui_name="Size2"\
      }:bit_fields.B_WREN2={\
        position=2:size=1:enum=E_WREN:gui_name="WREN2"\
      }:bit_fields.B_SSRAM2={\
        position=3:enum=E_SSRAM:gui_name="Type2"\
      }:bit_fields.B_WAIT2={\
        position=4:size=4:enum=E_WAIT:gui_name="Wait2"\
      }\
    }:Register.G_EBI_CSR3={\
      start=0x1200000C:length=4:gui_name="CSR3":bit_fields.B_MEMSIZE3={\
        size=2:enum=E_MEMSIZE:gui_name="Size3"\
      }:bit_fields.B_WREN3={\
        position=2:size=1:enum=E_WREN:gui_name="WREN3"\
      }:bit_fields.B_SSRAM3={\
        position=3:enum=E_SSRAM:gui_name="Type3"\
      }:bit_fields.B_WAIT3={\
        position=4:size=4:enum=E_WAIT:gui_name="Wait3"\
      }\