# CM922TEXCAL.BCD file. This file contains the board definition for the
# ARM922T XA10 Core Module with 4 Cross-Trigger Channels
#
# Copyright 2001-2003 ARM Limited.
[BOARD=CM922T-XA10-4XTRIG] 
Advanced_Information.ARM922T={\
  Memory_block.default={}:Map_rule.default={}:Register_enum.default={}:\
        Register.default={\
    bit_fields.default={}\
  }:Concat_Register.default={}:Peripherals.default={\
    Register.default={\
      bit_fields.default={}\
    }\
  }:Register_Window.default={}:ARM_config={}:\
        Cross_trigger.trig_in_ena="$1$ ce @B_DBGREQINEN |= 1":\
        Cross_trigger.trig_in_ena="$2$ ce @B_DBGREQINEN |= 2":\
        Cross_trigger.trig_in_ena="$3$ ce @B_DBGREQINEN |= 4":\
        Cross_trigger.trig_in_ena="$4$ ce @B_DBGREQINEN |= 8":\
        Cross_trigger.trig_in_dis="$1$ ce @B_DBGREQINEN &= ~1":\
        Cross_trigger.trig_in_dis="$2$ ce @B_DBGREQINEN &= ~2":\
        Cross_trigger.trig_in_dis="$3$ ce @B_DBGREQINEN &= ~4":\
        Cross_trigger.trig_in_dis="$4$ ce @B_DBGREQINEN &= ~8":\
        Cross_trigger.trig_out_ena="$1$ ce @B_DBGACKOUTEN |= 1":\
        Cross_trigger.trig_out_ena="$2$ ce @B_DBGACKOUTEN |= 2":\
        Cross_trigger.trig_out_ena="$3$ ce @B_DBGACKOUTEN |= 4":\
        Cross_trigger.trig_out_ena="$4$ ce @B_DBGACKOUTEN |= 8":\
        Cross_trigger.trig_out_dis="$1$ ce @B_DBGACKOUTEN &= ~1":\
        Cross_trigger.trig_out_dis="$2$ ce @B_DBGACKOUTEN &= ~2":\
        Cross_trigger.trig_out_dis="$3$ ce @B_DBGACKOUTEN &= ~4":\
        Cross_trigger.trig_out_dis="$4$ ce @B_DBGACKOUTEN &= ~8"\
}
description="CM922T-XA10 with 4 Cross-Trigger Channels"
boardChip_name=CM922T-XA10

[BOARD=CM922T-XA10] 
description="CM922T-XA10"
Advanced_Information.ARM922T={\
  Memory_block.M_CM_Regs={\
    start=0x10000000:length=0x1000000:type=default:wait_states=1:\
        description="CM Registers"\
  }:Memory_block.M_BootROM={\
    start=0x0000:length=0x40000:access=ROM:wait_states=5:description="Boot"\
  }:Memory_block.M_SSRAM={\
    start=0x0000:length=0x40000:wait_states=1:description="SSRAM"\
  }:Memory_block.M_Abort={\
    start=0x11000000:length=0xEF000000:access=NOMEM\
  }:Memory_block.M_SDRAM={\
    start=0x40000:length=0xFFC0000:wait_states=3:description="SDRAM"\
  }:Memory_block.M_Stripe={\
    start=0xB000000:length=0x4000:type=default:wait_states=3:\
        description="Stripe Regs":Attributes.volatile=True\
  }:Map_rule.R_MBDET={\
    register=G_CM_CTRL:mask=0x0002:value=0x0002:on_equal=M_SSRAM\
  }:Map_rule.R_NMBDET_REMAP={\
    register=G_CM_CTRL:mask=0x0006:value=0x0004:on_equal=M_SSRAM\
  }:Map_rule.R_NMBDET_NREMAP={\
    register=G_CM_CTRL:mask=0x0006:value=0x0000:on_equal=M_BootROM\
  }:Map_rule.R_Abort={\
    register=G_CM_CTRL:mask=0x0002:value=0x0002:on_equal=M_Abort\
  }:Map_rule.R_SDRAM={\
    register=G_CM_SDRAM:mask=0x0020:value=0x0020:on_equal=M_SDRAM\
  }:Register_enum.E_ENABLE={\
    names="DISABLED,ENABLED"\
  }:Register_enum.E_MBDET={\
    names="PRESENT,STANDALONE"\
  }:Register_enum.E_ON={\
    names="Off,On"\
  }:Register_enum.E_CASLAT={\
    names="DDR 2.5 cycles,resvd,2 cycles,3 cycles"\
  }:Register_enum.E_SDMEMSIZE={\
    names="16MB,32MB,64MB,128MB,256MB,resvd,resvd,resvd"\
  }:Register_enum.E_READY={\
    names="not avail.,ready"\
  }:Register_enum.E_SI_ID={\
    names="unknown,Lucent,LSI_G11,LSI_G12,resvd"\
  }:Register_enum.E_BIGEND={\
    names="little,big"\
  }:Register_enum.E_DIMM={\
    names="...,...,...,...,...,...,...,...,16MB,32MB,64MB,128MB,256MB,...,...,..."\
  }:Register_enum.E_VECTORS={\
    names="0x00000000,0xFFFF0000"\
  }:Register_enum.E_ID={\
    names="CM0,CM1,CM2,CM3"\
  }:Register_enum.E_OSC_OD={\
    names="div10,div2,div8,div4,div5,div7,div3,div6"\
  }:Register_enum.E_OSC_VDW={\
    names="1,2,3"\
  }:Register_enum.E_EBIWP={\
    names="Protected,Unprotected"\
  }:Register_enum.E_DPSRAM_MODE={\
    names="Normal Dual,Deep Single,Wide Single,reserved"\
  }:Register_enum.E_IOCR_IO={\
    names="PLD,Stripe"\
  }:Register_enum.E_IOCR_OC={\
    names="Slow,Fast,PCI Slow,PCI Fast,Open Slow,Open Fast,Open PCI Slow,Open PCI \
        Fast"\
  }:Register_enum.E_IOCR_IC={\
    names="2.5/3.3V LVTTL,1.8V LVTTL,SSTL_3/GTL+,Reserved"\
  }:Register_enum.E_HTRANS={\
    names="IDLE,BUSY,NONSEQ,SEQ"\
  }:Register_enum.E_HSIZE={\
    names="8,16,32,64,128,256,512,1024"\
  }:Register_enum.E_HBURST={\
    names="SINGLE,INCR,WRAP4,INCR4,WRAP8,INCR8,WRAP16,INCR16"\
  }:Register_enum.E_TIMEMODE={\
    names="FREE RUNNING,ONE SHOT,SW INTERVAL,RESERVED"\
  }:Register_enum.E_CHARLNG={\
    names="5,6,7,8"\
  }:Register_enum.E_PARITY={\
    names="OFF,ODD,OFF,EVEN,OFF,ALWAYS 1,OFF,ALWAYS 0"\
  }:Register_enum.E_STOPBIT={\
    names="1,2"\
  }:Register_enum.E_INTMODE={\
    names="6 priority,5 priority/1 individual,6 individual,6 individual"\
  }:Register.G_CM_ID={\
    start=0x0000:length=4:base=M_CM_Regs:type=unsigned:read_only=True:\
        gui_name="ID":bit_fields.B_REV_A={\
      size=4:gui_name="REV"\
    }:bit_fields.B_BUILD_A={\
      position=4:size=8:gui_name="Build"\
    }:bit_fields.B_FPGA_A={\
      position=12:size=4:gui_name="FPGA"\
    }:bit_fields.B_ARCH_A={\
      position=16:size=8:gui_name="ARCH"\
    }:bit_fields.B_MAN_A={\
      position=24:size=8:gui_name="MAN"\
    }\
  }:Register.G_CM_PROC={\
    start=0x0004:length=4:base=M_CM_Regs:type=unsigned:read_only=True:\
        gui_name="Processor":bit_fields.B_REV_A={\
      position=0:size=3:gui_name="REV"\
    }:bit_fields.B_PART_A={\
      position=4:size=12:gui_name="Part"\
    }:bit_fields.B_ARCH_A={\
      position=16:size=8:gui_name="ARCH"\
    }:bit_fields.B_IMP_A={\
      position=24:size=8:gui_name="Implementor"\
    }\
  }:Register.G_CM_OSC={\
    start=0x0008:length=4:base=M_CM_Regs:type=unsigned:gui_name="Oscillators":\
        bit_fields.B_OSCAVDW={\
      size=8:gui_name="Osc A VDW"\
    }:bit_fields.B_OSCAOD={\
      position=8:size=3:enum=E_OSC_OD:gui_name="Osc A OD"\
    }:bit_fields.B_OSCBVDW={\
      position=12:size=8:gui_name="Osc B VDW"\
    }:bit_fields.B_OSCBOD={\
      position=20:size=3:enum=E_OSC_OD:gui_name="Osc B OD"\
    }:bit_fields.B_OSCBUSM={\
      position=23:size=2:gui_name="Memory Bus Mode"\
    }\
  }:Register.G_CM_CTRL={\
    start=0x000C:length=4:base=M_CM_Regs:gui_name="Control":bit_fields.B_MISCLED_A={\
      position=0:size=1:enum=E_ON:read_only=False:gui_name="Misc.LED"\
    }:bit_fields.B_NMBDET_A={\
      position=1:enum=E_MBDET:read_only=True:gui_name="Motherboard"\
    }:bit_fields.B_REMAP_A={\
      position=2:enum=E_ENABLE:gui_name="Remap"\
    }:bit_fields.B_RESET_A={\
      position=3:size=1:read_only=True:gui_name="CM Reset"\
    }:bit_fields.B_USRLED0_A={\
      position=24:enum=E_ON:read_only=False:gui_name="USRLED0"\
    }:bit_fields.B_USRLED1_A={\
      position=25:enum=E_ON:read_only=False:gui_name="USRLED1"\
    }:bit_fields.B_USRLED2_A={\
      position=26:enum=E_ON:gui_name="USRLED2"\
    }:bit_fields.B_USRLED3_A={\
      position=27:enum=E_ON:gui_name="USRLED3"\
    }:bit_fields.B_USRLED4_A={\
      position=28:enum=E_ON:gui_name="USRLED4"\
    }:bit_fields.B_USRLED5_A={\
      position=29:enum=E_ON:gui_name="USRLED5"\
    }:bit_fields.B_USRLED6_A={\
      position=30:enum=E_ON:gui_name="USRLED6"\
    }:bit_fields.B_USRLED7_A={\
      position=31:enum=E_ON:gui_name="USRLED7"\
    }:bit_fields.B_EBIWP_A={\
      position=20:enum=E_EBIWP:gui_name="EBI 1&2 Write Protect"\
    }\
  }:Register.G_CM_STAT={\
    start=0x0010:length=4:base=M_CM_Regs:memory_type=default:read_only=True:\
        gui_name="Status":bit_fields.B_ID_A={\
      size=8:signed=False:enum=E_ID:read_only=True:gui_name="CM"\
    }:bit_fields.B_SI_ID_A={\
      position=8:size=8:signed=False:enum=E_SI_ID:read_only=True:gui_name="Man.ID"\
    }:bit_fields.B_SSRAMSIZE_A={\
      position=16:size=8:read_only=True:gui_name="SSRAM"\
    }:bit_fields.B_USRSW0_A={\
      position=24:enum=E_ON:read_only=True:gui_name="USRSW0"\
    }:bit_fields.B_USRSW1_A={\
      position=25:enum=E_ON:read_only=True:gui_name="USRSW1"\
    }:bit_fields.B_USRSW2_A={\
      position=26:enum=E_ON:read_only=True:gui_name="USRSW2"\
    }:bit_fields.B_USRSW3_A={\
      position=27:enum=E_ON:read_only=True:gui_name="USRSW3"\
    }:bit_fields.B_USRSW4_A={\
      position=28:enum=E_ON:read_only=True:gui_name="USRSW4"\
    }:bit_fields.B_USRSW5_A={\
      position=29:enum=E_ON:read_only=True:gui_name="USRSW5"\
    }:bit_fields.B_USRSW6_A={\
      position=30:enum=E_ON:read_only=True:gui_name="USRSW6"\
    }:bit_fields.B_USRSW7_A={\
      position=31:enum=E_ON:read_only=True:gui_name="USRSW7"\
    }\
  }:Register.G_CM_LOCK={\
    start=0x0014:length=4:base=M_CM_Regs:gui_name="Lock":bit_fields.B_LOCKVAL_A={\
      size=16:read_only=False:gui_name="Lock Value"\
    }:bit_fields.B_LOCKED_A={\
      position=16:enum=E_ENABLE:read_only=True:gui_name="Lock Osc."\
    }\
  }:Register.G_CM_LMBUSCNT={\
    start=0x0018:length=4:base=M_CM_Regs:read_only=True:\
        gui_name="Bus Cycle Counter":bit_fields.default={}\
  }:Register.G_CM_SDRAM={\
    start=0x0020:length=4:base=M_CM_Regs:gui_name="SDRAM":bit_fields.B_CASLAT={\
      size=2:enum=E_CASLAT:gui_name="CAS Latency"\
    }:bit_fields.B_MEMSIZE={\
      position=2:size=3:enum=E_SDMEMSIZE:gui_name="MEMSIZE"\
    }:bit_fields.B_SPDOK={\
      position=5:gui_name="SPDOK"\
    }:bit_fields.B_NROWS={\
      position=8:size=4:gui_name="rows"\
    }:bit_fields.B_NCOLS={\
      position=12:size=4:gui_name="columns"\
    }:bit_fields.B_NBANKS={\
      position=16:size=4:gui_name="banks"\
    }:bit_fields.B_DIMM={\
      position=2:size=4:enum=E_DIMM:gui_name="DIMM"\
    }\
  }:Register.G_CM_REFCNT={\
    start=0x0028:length=4:base=M_CM_Regs:read_only=True:\
        gui_name="Reference Clock Cycle Counter":bit_fields.default={}\
  }:Register.G_CM_FLAGS={\
    start=0x0030:length=4:base=M_CM_Regs:read_only=True:gui_name="Flags":\
        bit_fields.default={}\
  }:Register.G_CM_FLAGSS={\
    start=0x0030:length=4:base=M_CM_Regs:gui_name="Set":bit_fields.default={}\
  }:Register.G_CM_FLAGSC={\
    start=0x0034:length=4:base=M_CM_Regs:gui_name="Clear":bit_fields.default={}\
  }:Register.G_CM_NVFLAGS={\
    start=0x0038:length=4:base=M_CM_Regs:read_only=True:\
        gui_name="Nonvolatile Flags":bit_fields.default={}\
  }:Register.G_CM_NVFLAGSS={\
    start=0x0038:length=4:base=M_CM_Regs:gui_name="nvSet":bit_fields.default={}\
  }:Register.G_CM_NVFLAGSC={\
    start=0x003C:length=4:base=M_CM_Regs:read_only=False:gui_name="nvClear":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_STAT={\
    start=0x0040:length=1:base=M_CM_Regs:read_only=True:gui_name="Status":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_RSTAT={\
    start=0x0044:length=1:base=M_CM_Regs:read_only=True:gui_name="Raw Status":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_ENSET={\
    start=0x0048:length=1:base=M_CM_Regs:gui_name="Enable Set":bit_fields.default={}\
  }:Register.G_CM_IRQ_ENCLR={\
    start=0x004C:length=1:base=M_CM_Regs:gui_name="Enable Clear":\
        bit_fields.default={}\
  }:Register.G_CM_SOFT_INTSET={\
    start=0x0050:length=1:base=M_CM_Regs:gui_name="Set":bit_fields.default={}\
  }:Register.G_CM_SOFT_INTCLR={\
    start=0x0054:length=1:base=M_CM_Regs:gui_name="Clear":bit_fields.default={}\
  }:Register.G_CM_FIQ_STAT={\
    start=0x0060:length=1:base=M_CM_Regs:read_only=True:gui_name="Status":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_RSTAT={\
    start=0x0064:length=1:base=M_CM_Regs:read_only=True:gui_name="Raw Status":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_ENSET={\
    start=0x0068:length=1:base=M_CM_Regs:gui_name="Enable Set":bit_fields.default={}\
  }:Register.G_CM_FIQ_ENCLR={\
    start=0x006C:length=1:base=M_CM_Regs:gui_name="Enable Clear":\
        bit_fields.default={}\
  }:Register.G_CM_DBGXTRIG={\
    start=0x0070:length=4:base=M_CM_Regs:gui_name="Debug Xtrigger":\
        bit_fields.B_DBGACKSOFT={\
      size=4:gui_name="DBGACKSOFT"\
    }:bit_fields.B_DBGACKSOFTEN={\
      position=4:size=4:gui_name="DBGACKSOFTEN"\
    }:bit_fields.B_DBGACKOUTEN={\
      position=8:size=4:gui_name="DBGACKOUTEN"\
    }:bit_fields.B_DBGREQINEN={\
      position=12:size=4:gui_name="DBGREQINEN"\
    }\
  }:Register.G_SR_BOOT_CR={\
    start=0x0000:length=4:base=M_Stripe:gui_name="Boot Control":\
        bit_fields.B_BOOTCR_BM={\
      gui_name="Boot Mem Map"\
    }:bit_fields.B_BOOTCR_HM={\
      position=1:gui_name="Hold uproc"\
    }:bit_fields.B_BOOTCR_RE={\
      position=2:gui_name="Regs Enabled"\
    }\