# CM720T.BCD file. This file contains the board definition for the
# ARM720T Core Module with 1 Cross-Trigger Channel
#
# Copyright 2001-2003 ARM Limited.
[BOARD=CM720T-1XTRIG] 
description="CM720T with 1 Cross-Trigger Channel"
boardChip_name=CM720T
Advanced_Information.ARM720T={\
  Memory_block.default={}:Map_rule.default={}:Register_enum.default={}:\
        Register.default={\
    bit_fields.default={}\
  }:Concat_Register.default={}:Peripherals.default={\
    Register.default={\
      bit_fields.default={}\
    }\
  }:Register_Window.default={}:ARM_config={}:\
        Cross_trigger.trig_in_ena="ce @B_DBGREQINEN |= 1":\
        Cross_trigger.trig_in_dis="ce @B_DBGREQINEN &= ~1":\
        Cross_trigger.trig_out_ena="ce @B_DBGACKOUTEN |= 1":\
        Cross_trigger.trig_out_dis="ce @B_DBGACKOUTEN &= ~1"\
}

[BOARD=CM720T] 
Advanced_Information.ARM720T={\
  Memory_block.M_CM_Regs={\
    start=0x10000000:length=0x1000000:wait_states=1:description="CM Registers"\
  }:Memory_block.M_BootROM={\
    start=0x0000:length=0x40000:access=ROM:wait_states=5:description="Boot"\
  }:Memory_block.M_SSRAM={\
    start=0x0000:length=0x40000:wait_states=1:description="SSRAM"\
  }:Memory_block.M_Abort={\
    start=0x11000000:length=0xEF000000:access=NOMEM\
  }:Memory_block.M_SDRAM={\
    start=0x40000:length=0xFFC0000:wait_states=3:description="SDRAM"\
  }:Map_rule.R_MBDET={\
    register=G_CM_CTRL:mask=0x0002:value=0x0002:on_equal=M_SSRAM\
  }:Map_rule.R_NMBDET_REMAP={\
    register=G_CM_CTRL:mask=0x0006:value=0x0004:on_equal=M_SSRAM\
  }:Map_rule.R_NMBDET_NREMAP={\
    register=G_CM_CTRL:mask=0x0006:value=0x0000:on_equal=M_BootROM\
  }:Map_rule.R_Abort={\
    register=G_CM_CTRL:mask=0x0002:value=0x0002:on_equal=M_Abort\
  }:Map_rule.R_SDRAM={\
    register=G_CM_SDRAM:mask=0x0020:value=0x0020:on_equal=M_SDRAM\
  }:Register_enum.E_ENABLE={\
    names="DISABLED,ENABLED"\
  }:Register_enum.E_MBDET={\
    names="PRESENT,STANDALONE"\
  }:Register_enum.E_ON={\
    names="Off,On"\
  }:Register_enum.E_CASLAT={\
    names="resvd,resvd,2 cycles,3 cycles"\
  }:Register_enum.E_SDMEMSIZE={\
    names="16MB,32MB,64MB,128MB,256MB,resvd,resvd,resvd"\
  }:Register_enum.E_READY={\
    names="not avail.,ready"\
  }:Register_enum.E_OD={\
    names="10,2,8,4,5,7,9,6"\
  }:Register_enum.E_FASTBUS={\
    names="asynchronous,FastBus"\
  }:Register_enum.E_DIMM={\
    names="...,...,...,...,...,...,...,...,16MB,32MB,64MB,128MB,256MB,...,...,..."\
  }:Register_enum.E_ID={\
    names="0,1,2,3"\
  }:Register.G_CM_ID={\
    start=0x0000:length=4:base=M_CM_Regs:type=unsigned:read_only=True:\
        gui_name="ID":bit_fields.B_REV_A={\
      size=4:gui_name="REV"\
    }:bit_fields.B_BUILD_A={\
      position=4:size=8:gui_name="Build"\
    }:bit_fields.B_FPGA_A={\
      position=12:size=4:gui_name="FPGA"\
    }:bit_fields.B_ARCH_A={\
      position=16:size=8:gui_name="ARCH"\
    }:bit_fields.B_MAN_A={\
      position=24:size=8:gui_name="MAN"\
    }\
  }:Register.G_CM_PROC={\
    start=0x0004:length=4:base=M_CM_Regs:type=unsigned:read_only=True:\
        gui_name="Processor":bit_fields.default={}\
  }:Register.G_CM_OSC={\
    start=0x0008:length=4:base=M_CM_Regs:type=unsigned:gui_name="Oscillators":\
        bit_fields.B_C_VDW_A={\
      size=8:gui_name="Core Clock VCO Divider"\
    }:bit_fields.B_C_OD_A={\
      position=8:size=3:enum=E_OD:gui_name="Core Clock Output Divider"\
    }:bit_fields.B_L_VDW_A={\
      position=12:size=8:gui_name="Processor Bus Clock VCO Divider"\
    }:bit_fields.B_L_OD_A={\
      position=20:size=3:enum=E_OD:gui_name="Memory Clock Output Divider"\
    }:bit_fields.B_BMODE_A={\
      position=23:size=2:gui_name="Bus Mode"\
    }\
  }:Register.G_CM_CTRL={\
    start=0x000C:length=4:base=M_CM_Regs:gui_name="Control":bit_fields.B_LED_A={\
      position=0:size=1:enum=E_ON:read_only=False:gui_name="Misc.LED"\
    }:bit_fields.B_NMBDET_A={\
      position=1:enum=E_MBDET:read_only=True:gui_name="Motherboard"\
    }:bit_fields.B_REMAP_A={\
      position=2:enum=E_ENABLE:gui_name="Remap"\
    }:bit_fields.B_RESET_A={\
      position=3:size=1:enum=E_ENABLE:read_only=False:gui_name="CM Reset"\
    }:bit_fields.B_CM_FASTBUS={\
      position=6:enum=E_FASTBUS:gui_name="Bus (7x0T)"\
    }\
  }:Register.G_CM_STAT={\
    start=0x0010:length=4:base=M_CM_Regs:read_only=True:gui_name="Status":\
        bit_fields.B_ID_A={\
      size=8:signed=False:enum=E_ID:read_only=True:gui_name="Position"\
    }:bit_fields.B_SSRAM_A={\
      position=16:size=8:read_only=True:gui_name="SSRAM"\
    }\
  }:Register.G_CM_LOCK={\
    start=0x0014:length=4:base=M_CM_Regs:gui_name="Lock":bit_fields.B_LOCKVAL_A={\
      size=16:read_only=False:gui_name="Lock Value"\
    }:bit_fields.B_LOCKED_A={\
      position=16:enum=E_ENABLE:read_only=True:gui_name="Osc.Reg Locked"\
    }\
  }:Register.G_CM_SDRAM={\
    start=0x0020:length=4:base=M_CM_Regs:read_only=True:gui_name="SDRAM":\
        bit_fields.B_CASLAT={\
      size=2:enum=E_CASLAT:read_only=False:gui_name="CAS latency"\
    }:bit_fields.B_MEMSIZE={\
      position=2:size=3:enum=E_SDMEMSIZE:gui_name="MEMSIZE"\
    }:bit_fields.B_SPDOK={\
      position=5:enum=E_READY:read_only=True:gui_name="SPDOK"\
    }:bit_fields.B_NROWS={\
      position=8:size=4:gui_name="#rows"\
    }:bit_fields.B_NCOLS={\
      position=12:size=4:gui_name="#columns"\
    }:bit_fields.B_NBANKS={\
      position=16:size=4:gui_name="#banks"\
    }:bit_fields.B_DIMM={\
      position=2:size=4:enum=E_DIMM:read_only=True:gui_name="DIMM"\
    }\
  }:Register.G_CM_IRQ_STAT={\
    start=0x0040:length=4:base=M_CM_Regs:read_only=True:gui_name="IRQ Status":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_RSTAT={\
    start=0x0044:length=4:base=M_CM_Regs:read_only=True:gui_name="IRQ Raw Status":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_ENSET={\
    start=0x0048:length=4:base=M_CM_Regs:gui_name="IRQ Enable Set":\
        bit_fields.default={}\
  }:Register.G_CM_IRQ_ENCLR={\
    start=0x004C:length=4:base=M_CM_Regs:gui_name="IRQ Enable Clear":\
        bit_fields.default={}\
  }:Register.G_CM_SOFT_INTSET={\
    start=0x0050:length=4:base=M_CM_Regs:gui_name="Software Interrupt Set":\
        bit_fields.default={}\
  }:Register.G_CM_SOFT_INTCLR={\
    start=0x0054:length=4:base=M_CM_Regs:gui_name="Software Interrupt Clear":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_STAT={\
    start=0x0060:length=4:base=M_CM_Regs:read_only=True:gui_name="FIQ Status":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_RSTAT={\
    start=0x0064:length=4:base=M_CM_Regs:read_only=True:gui_name="FIQ Raw Status":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_ENSET={\
    start=0x0068:length=4:base=M_CM_Regs:gui_name="FIQ Enable Set":\
        bit_fields.default={}\
  }:Register.G_CM_FIQ_ENCLR={\
    start=0x006C:length=4:base=M_CM_Regs:gui_name="FIQ Enable Clear":\
        bit_fields.default={}\
  }:Register.G_CM_DBGXTRIG={\
    start=0x0070:length=4:base=M_CM_Regs:gui_name="Debug Xtrigger":\
        bit_fields.B_DBGACKSOFT={\
      size=4:gui_name="DBGACKSOFT"\
    }:bit_fields.B_DBGACKSOFTEN={\
      position=4:size=4:gui_name="DBGACKSOFTEN"\
    }:bit_fields.B_DBGACKOUTEN={\
      position=8:size=4:gui_name="DBGACKOUTEN"\
    }:bit_fields.B_DBGREQINEN={\
      position=12:size=4:gui_name="DBGREQINEN"\
    }\
  }:Register.G_CM_SPD={\
    start=0x0100:length=256:base=M_CM_Regs:read_only=True:\
        gui_name="SDRAM SPD Memory":bit_fields.default={}\
  }:Concat_Register.default={}:Peripherals.default={\
    Register.default={\
      bit_fields.default={}\
    }\
  }:Register_Window.CM720T={\
    line="B_NMBDET_A,B_REMAP_A,B_LED_A":line="=B_ID_A,B_DIMM":line="_":line="$+":\
        line="_ID":line="B_MAN_A,B_ARCH_A,B_FPGA_A,B_BUILD_A,B_REV_A":\
        line="=G_CM_PROC":line="$+":line="_Oscillator":line="=B_BMODE_A":\
        line="=B_L_OD_A":line="=B_L_VDW_A":line="=B_LOCKED_A":line="=B_LOCKVAL_A":\
        line="$+":line="_Control":line="=B_RESET_A":line="=B_CM_FASTBUS":line="$+":\
        line="_SDRAM":line="=B_NBANKS":line="=B_NCOLS":line="=B_NROWS":line="=B_SPDOK":\
        line="=B_MEMSIZE":line="=B_CASLAT":line="$+":line="_IRQ":line="=G_CM_IRQ_STAT":\
        line="=G_CM_IRQ_RSTAT":line="=G_CM_IRQ_ENSET":line="=G_CM_IRQ_ENCLR":line="$+":\
        line="_Soft IRQ":line="=G_CM_SOFT_INTSET":line="=G_CM_SOFT_INTCLR":line="$+":\
        line="_FIQ":line="=G_CM_FIQ_STAT":line="=G_CM_FIQ_RSTAT":\
        line="=G_CM_FIQ_ENSET":line="=G_CM_FIQ_ENCLR"\
  }:ARM_config={\
    top_memory=0x40000\
  }\
}
description="ARM720T Core Module"