?? bulkloop.lst
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262 =1 // Endpoint Buffers
263 =1
264 =1 EXTERN xdata volatile BYTE EP0BUF[64] _AT_ 0xE740; // EP0 IN-OUT buffer
265 =1 EXTERN xdata volatile BYTE EP1OUTBUF[64] _AT_ 0xE780; // EP1-OUT buffer
266 =1 EXTERN xdata volatile BYTE EP1INBUF[64] _AT_ 0xE7C0; // EP1-IN buffer
267 =1 EXTERN xdata volatile BYTE EP2FIFOBUF[1024] _AT_ 0xF000; // 512/1024-byte EP2 buffer (IN or OUT)
268 =1 EXTERN xdata volatile BYTE EP4FIFOBUF[1024] _AT_ 0xF400; // 512 byte EP4 buffer (IN or OUT)
269 =1 EXTERN xdata volatile BYTE EP6FIFOBUF[1024] _AT_ 0xF800; // 512/1024-byte EP6 buffer (IN or OUT)
270 =1 EXTERN xdata volatile BYTE EP8FIFOBUF[1024] _AT_ 0xFC00; // 512 byte EP8 buffer (IN or OUT)
271 =1
272 =1 #undef EXTERN
273 =1 #undef _AT_
274 =1
275 =1 /*-----------------------------------------------------------------------------
276 =1 Special Function Registers (SFRs)
277 =1 The byte registers and bits defined in the following list are based
278 =1 on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
279 =1 If you modify the register definitions below, please regenerate the file
280 =1 "ezregs.inc" which includes the same basic information for assembly inclusion.
281 =1 -----------------------------------------------------------------------------*/
282 =1
283 =1 sfr IOA = 0x80;
284 =1 sfr SP = 0x81;
285 =1 sfr DPL = 0x82;
286 =1 sfr DPH = 0x83;
287 =1 sfr DPL1 = 0x84;
288 =1 sfr DPH1 = 0x85;
289 =1 sfr DPS = 0x86;
290 =1 /* DPS */
291 =1 sbit SEL = 0x86+0;
292 =1 sfr PCON = 0x87; /* PCON */
293 =1 //sbit IDLE = 0x87+0;
294 =1 //sbit STOP = 0x87+1;
295 =1 //sbit GF0 = 0x87+2;
296 =1 //sbit GF1 = 0x87+3;
C51 COMPILER V7.50 BULKLOOP 04/01/2005 11:24:34 PAGE 12
297 =1 //sbit SMOD0 = 0x87+7;
298 =1 sfr TCON = 0x88;
299 =1 /* TCON */
300 =1 sbit IT0 = 0x88+0;
301 =1 sbit IE0 = 0x88+1;
302 =1 sbit IT1 = 0x88+2;
303 =1 sbit IE1 = 0x88+3;
304 =1 sbit TR0 = 0x88+4;
305 =1 sbit TF0 = 0x88+5;
306 =1 sbit TR1 = 0x88+6;
307 =1 sbit TF1 = 0x88+7;
308 =1 sfr TMOD = 0x89;
309 =1 /* TMOD */
310 =1 //sbit M00 = 0x89+0;
311 =1 //sbit M10 = 0x89+1;
312 =1 //sbit CT0 = 0x89+2;
313 =1 //sbit GATE0 = 0x89+3;
314 =1 //sbit M01 = 0x89+4;
315 =1 //sbit M11 = 0x89+5;
316 =1 //sbit CT1 = 0x89+6;
317 =1 //sbit GATE1 = 0x89+7;
318 =1 sfr TL0 = 0x8A;
319 =1 sfr TL1 = 0x8B;
320 =1 sfr TH0 = 0x8C;
321 =1 sfr TH1 = 0x8D;
322 =1 sfr CKCON = 0x8E;
323 =1 /* CKCON */
324 =1 //sbit MD0 = 0x89+0;
325 =1 //sbit MD1 = 0x89+1;
326 =1 //sbit MD2 = 0x89+2;
327 =1 //sbit T0M = 0x89+3;
328 =1 //sbit T1M = 0x89+4;
329 =1 //sbit T2M = 0x89+5;
330 =1 sfr SPC_FNC = 0x8F; // Was WRS in Reg320
331 =1 /* CKCON */
332 =1 //sbit WRS = 0x8F+0;
333 =1 sfr IOB = 0x90;
334 =1 sfr EXIF = 0x91; // EXIF Bit Values differ from Reg320
335 =1 /* EXIF */
336 =1 //sbit USBINT = 0x91+4;
337 =1 //sbit I2CINT = 0x91+5;
338 =1 //sbit IE4 = 0x91+6;
339 =1 //sbit IE5 = 0x91+7;
340 =1 sfr MPAGE = 0x92;
341 =1 sfr SCON0 = 0x98;
342 =1 /* SCON0 */
343 =1 sbit RI = 0x98+0;
344 =1 sbit TI = 0x98+1;
345 =1 sbit RB8 = 0x98+2;
346 =1 sbit TB8 = 0x98+3;
347 =1 sbit REN = 0x98+4;
348 =1 sbit SM2 = 0x98+5;
349 =1 sbit SM1 = 0x98+6;
350 =1 sbit SM0 = 0x98+7;
351 =1 sfr SBUF0 = 0x99;
352 =1
353 =1 sfr APTR1H = 0x9A; // old name
354 =1 sfr APTR1L = 0x9B; // old name
355 =1 sfr AUTOPTR1H = 0x9A;
356 =1 sfr AUTOPTR1L = 0x9B;
357 =1 sfr AUTOPTRH2 = 0x9D;
358 =1 sfr AUTOPTRL2 = 0x9E;
C51 COMPILER V7.50 BULKLOOP 04/01/2005 11:24:34 PAGE 13
359 =1 sfr IOC = 0xA0;
360 =1 sfr INT2CLR = 0xA1;
361 =1 sfr INT4CLR = 0xA2;
362 =1
363 =1 sfr IE = 0xA8;
364 =1 /* IE */
365 =1 sbit EX0 = 0xA8+0;
366 =1 sbit ET0 = 0xA8+1;
367 =1 sbit EX1 = 0xA8+2;
368 =1 sbit ET1 = 0xA8+3;
369 =1 sbit ES0 = 0xA8+4;
370 =1 sbit ET2 = 0xA8+5;
371 =1 sbit ES1 = 0xA8+6;
372 =1 sbit EA = 0xA8+7;
373 =1
374 =1 sfr EP2468STAT = 0xAA;
375 =1 /* EP2468STAT */
376 =1 //sbit EP2E = 0xAA+0;
377 =1 //sbit EP2F = 0xAA+1;
378 =1 //sbit EP4E = 0xAA+2;
379 =1 //sbit EP4F = 0xAA+3;
380 =1 //sbit EP6E = 0xAA+4;
381 =1 //sbit EP6F = 0xAA+5;
382 =1 //sbit EP8E = 0xAA+6;
383 =1 //sbit EP8F = 0xAA+7;
384 =1
385 =1 sfr EP24FIFOFLGS = 0xAB;
386 =1 sfr EP68FIFOFLGS = 0xAC;
387 =1 sfr AUTOPTRSETUP = 0xAF;
388 =1 /* AUTOPTRSETUP */
389 =1 sbit EXTACC = 0xAF+0;
390 =1 sbit APTR1FZ = 0xAF+1;
391 =1 sbit APTR2FZ = 0xAF+2;
392 =1
393 =1 sfr IOD = 0xB0;
394 =1 sfr IOE = 0xB1;
395 =1 sfr OEA = 0xB2;
396 =1 sfr OEB = 0xB3;
397 =1 sfr OEC = 0xB4;
398 =1 sfr OED = 0xB5;
399 =1 sfr OEE = 0xB6;
400 =1
401 =1 sfr IP = 0xB8;
402 =1 /* IP */
403 =1 sbit PX0 = 0xB8+0;
404 =1 sbit PT0 = 0xB8+1;
405 =1 sbit PX1 = 0xB8+2;
406 =1 sbit PT1 = 0xB8+3;
407 =1 sbit PS0 = 0xB8+4;
408 =1 sbit PT2 = 0xB8+5;
409 =1 sbit PS1 = 0xB8+6;
410 =1
411 =1 sfr EP01STAT = 0xBA;
412 =1 sfr GPIFTRIG = 0xBB;
413 =1
414 =1 sfr GPIFSGLDATH = 0xBD;
415 =1 sfr GPIFSGLDATLX = 0xBE;
416 =1 sfr GPIFSGLDATLNOX = 0xBF;
417 =1
418 =1 sfr SCON1 = 0xC0;
419 =1 /* SCON1 */
420 =1 sbit RI1 = 0xC0+0;
C51 COMPILER V7.50 BULKLOOP 04/01/2005 11:24:34 PAGE 14
421 =1 sbit TI1 = 0xC0+1;
422 =1 sbit RB81 = 0xC0+2;
423 =1 sbit TB81 = 0xC0+3;
424 =1 sbit REN1 = 0xC0+4;
425 =1 sbit SM21 = 0xC0+5;
426 =1 sbit SM11 = 0xC0+6;
427 =1 sbit SM01 = 0xC0+7;
428 =1 sfr SBUF1 = 0xC1;
429 =1 sfr T2CON = 0xC8;
430 =1 /* T2CON */
431 =1 sbit CP_RL2 = 0xC8+0;
432 =1 sbit C_T2 = 0xC8+1;
433 =1 sbit TR2 = 0xC8+2;
434 =1 sbit EXEN2 = 0xC8+3;
435 =1 sbit TCLK = 0xC8+4;
436 =1 sbit RCLK = 0xC8+5;
437 =1 sbit EXF2 = 0xC8+6;
438 =1 sbit TF2 = 0xC8+7;
439 =1 sfr RCAP2L = 0xCA;
440 =1 sfr RCAP2H = 0xCB;
441 =1 sfr TL2 = 0xCC;
442 =1 sfr TH2 = 0xCD;
443 =1 sfr PSW = 0xD0;
444 =1 /* PSW */
445 =1 sbit P = 0xD0+0;
446 =1 sbit FL = 0xD0+1;
447 =1 sbit OV = 0xD0+2;
448 =1 sbit RS0 = 0xD0+3;
449 =1 sbit RS1 = 0xD0+4;
450 =1 sbit F0 = 0xD0+5;
451 =1 sbit AC = 0xD0+6;
452 =1 sbit CY = 0xD0+7;
453 =1 sfr EICON = 0xD8; // Was WDCON in DS80C320; Bit Values differ from Reg320
454 =1 /* EICON */
455 =1 sbit INT6 = 0xD8+3;
456 =1 sbit RESI = 0xD8+4;
457 =1 sbit ERESI = 0xD8+5;
458 =1 sbit SMOD1 = 0xD8+7;
459 =1 sfr ACC = 0xE0;
460 =1 sfr EIE = 0xE8; // EIE Bit Values differ from Reg320
461 =1 /* EIE */
462 =1 sbit EUSB = 0xE8+0;
463 =1 sbit EI2C = 0xE8+1;
464 =1 sbit EIEX4 = 0xE8+2;
465 =1 sbit EIEX5 = 0xE8+3;
466 =1 sbit EIEX6 = 0xE8+4;
467 =1 sfr B = 0xF0;
468 =1 sfr EIP = 0xF8; // EIP Bit Values differ from Reg320
469 =1 /* EIP */
470 =1 sbit PUSB = 0xF8+0;
471 =1 sbit PI2C = 0xF8+1;
472 =1 sbit EIPX4 = 0xF8+2;
473 =1 sbit EIPX5 = 0xF8+3;
474 =1 sbit EIPX6 = 0xF8+4;
475 =1
476 =1 /*-----------------------------------------------------------------------------
477 =1 Bit Masks
478 =1 -----------------------------------------------------------------------------*/
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