?? tyspci.c
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#include "vxworks.h"
/*********************pci1410a config resister define**********/
#define Device_ID 0x02
#define Vendor_ID 0x00
#define Command 0x04
#define Status 0x06
#define Revision_ID 0x08
#define PCI_class_code 0x09
#define BITS 0x0F
#define Header_type 0x0E
#define Latency_timer 0x0D
#define
Cache_line_size 0x0C
#define CardBus_socket 0x10
#define Secondary_status 0x16
#define Capability_pointer 0x14
#define CardBus_latency_timer 0x1B
#define Subordinate_bus_number 0x1A
#define CardBus_bus_number 0x19
#define PCI_bus_number 0x18
#define Memory_base_0 0x1C
#define Memory_limit_0 0x20
#define Memory_base_1 0x24
#define Memory_limit_1 0x28
#define IO_base_0 0x2C
#define IO_limit_0 0x30
#define IO_base_1 0x34
#define IO_limit_1 0x38
#define Bridge_control 0x3E
#define interrupt_pin 0x3D
#define interrupt_line 0x3C
#define Subsystem_ID 0x42
#define Subsystem_Vendor_ID 0x40
#define PC_Card_legacy_mode_base_addr 0x44
#define System_control 0x80
#define Multi_routing 0x8C
#define Diagnostic 0x93
#define Device_control 0x92
#define Card_control 0x91
#define Retry_status 0x90
#define Socket_DMA_register_0 0x94
#define Socket_DMA_register_1 0x98
#define Power_manage_capabilities 0xA2
#define Next_item 0xA1
#define Capability_ID 0xA0
#define Power_manage_data 0xA7
#define Power_manage_control 0xA4
#define Power_manage_extension 0xA6
#define General_purpose_event_enable 0xAA
#define General_purpose_event_status 0xA8
#define General_purpose_output 0xAE
#define General_purpose_inoput 0xAC
#define Serial_bus_control 0xB3
#define Serial_bus_slave 0xB2
#define Serial_bus_index 0xB1
#define Serial_bus_data 0xB0
#include"config.h"
#include "drv/pci/pciConfigShow.h"
#include "drv/pci/pciConfigLib.h"
#include "drv/pci/pciIntLib.h"
#include "ads8260.h"
#include "sysLib.h"
#include "mot82xxPci.h"
#include "drv/mem/m8260Memc.h"
#include "drv/mem/m8260Siu.h"
#include "drv/pci/pciAutoConfigLib.h"
#include "drv/pci/pciHeaderDefs.h"
#include "sysBusPci.h"
#define firVendorId 0x11C1
#define firDeviceId 0x5811
#define secVendorId 0x104C
#define secDeviceId 0xAC50
#define tys_CONFIG_ABSENT_F 0xffff
#define tys_CONFIG_ABSENT_0 0x0000
/* pciAutoConfig BSP support file */
IMPORT int sysPciOutLong(UINT32*,UINT32);
IMPORT UINT32 sysPciInLong (UINT32*);
LOCAL PCI_SYSTEM sysParams;
LOCAL int lastPciListSize;LOCAL PCI_LOC *pLastPciList;#define PCI_AUTO_MAX_FUNCTIONS 32
#define NO_ALLOCATION 0xffffffff
#define tys_MAX_BUS 255
int tysMaxBus = tys_MAX_BUS;
ULONG tyspciConfAddr =0x04710900;
ULONG tyspciConfData = 0x04710904;
#define M8260_DPPC_MASK 0x00000000 /* bits 4 and 5 */
#define M8260_DPPC_VALUE 0x00000000 /* bits (4,5) should be (1,0) */
LOCAL UCHAR tysAutoIntRoutingTable[4] = { (UCHAR) 0xff,
(UCHAR) 0xff, (UCHAR) 0xff, (UCHAR) 0xff };
LOCAL void tysBheaderPrint
( PCI_HEADER_BRIDGE * pB ) { printf ("vendor ID = 0x%.4x\n", (ushort_t)pB->vendorId); printf ("device ID = 0x%.4x\n", (ushort_t)pB->deviceId); printf ("command register = 0x%.4x\n", (ushort_t)pB->command); printf ("status register = 0x%.4x\n", (ushort_t)pB->status); printf ("revision ID = 0x%.2x\n", (uchar_t)pB->revisionId); printf ("class code = 0x%.2x\n", (uchar_t)pB->classCode); printf ("sub class code = 0x%.2x\n", (uchar_t)pB->subClass); printf ("programming interface = 0x%.2x\n", (uchar_t)pB->progIf); printf ("cache line = 0x%.2x\n", (uchar_t)pB->cacheLine); printf ("latency time = 0x%.2x\n", (uchar_t)pB->latency); printf ("header type = 0x%.2x\n", (uchar_t)pB->headerType); printf ("BIST = 0x%.2x\n", (uchar_t)pB->bist); printf ("base address 0 = 0x%.8x\n", pB->base0); printf ("base address 1 = 0x%.8x\n", pB->base1); printf ("primary bus number = 0x%.2x\n", (uchar_t)pB->priBus); printf ("secondary bus number = 0x%.2x\n", (uchar_t)pB->secBus); printf ("subordinate bus number = 0x%.2x\n", (uchar_t)pB->subBus); printf ("secondary latency timer = 0x%.2x\n", (uchar_t)pB->secLatency); printf ("IO base = 0x%.2x\n", (uchar_t)pB->ioBase); printf ("IO limit = 0x%.2x\n", (uchar_t)pB->ioLimit); printf ("secondary status = 0x%.4x\n", (ushort_t)pB->secStatus); printf ("memory base = 0x%.4x\n", (ushort_t)pB->memBase); printf ("memory limit = 0x%.4x\n", (ushort_t)pB->memLimit); printf ("prefetch memory base = 0x%.4x\n", (ushort_t)pB->preBase); printf ("prefetch memory limit = 0x%.4x\n", (ushort_t)pB->preLimit); printf ("prefetch memory base upper = 0x%.8x\n", pB->preBaseUpper); printf ("prefetch memory limit upper = 0x%.8x\n", pB->preLimitUpper); printf ("IO base upper 16 bits = 0x%.4x\n", (ushort_t)pB->ioBaseUpper); printf ("IO limit upper 16 bits = 0x%.4x\n", (ushort_t)pB->ioLimitUpper); printf ("expansion ROM base address = 0x%.8x\n", pB->romBase); printf ("interrupt line = 0x%.2x\n", (uchar_t)pB->intLine); printf ("interrupt pin = 0x%.2x\n", (uchar_t)pB->intPin); printf ("bridge control = 0x%.4x\n", (ushort_t)pB->control); }
LOCAL void tysDheaderPrint
( PCI_HEADER_DEVICE * pD ) { printf ("vendor ID = 0x%.4x\n", (ushort_t)pD->vendorId); printf ("device ID = 0x%.4x\n", (ushort_t)pD->deviceId); printf ("command register = 0x%.4x\n", (ushort_t)pD->command); printf ("status register = 0x%.4x\n", (ushort_t)pD->status); printf ("revision ID = 0x%.2x\n", (uchar_t)pD->revisionId); printf ("class code = 0x%.2x\n", (uchar_t)pD->classCode); printf ("sub class code = 0x%.2x\n", (uchar_t)pD->subClass); printf ("programming interface = 0x%.2x\n", (uchar_t)pD->progIf); printf ("cache line = 0x%.2x\n", (uchar_t)pD->cacheLine); printf ("latency time = 0x%.2x\n", (uchar_t)pD->latency); printf ("header type = 0x%.2x\n", (uchar_t)pD->headerType); printf ("BIST = 0x%.2x\n", (uchar_t)pD->bist); printf ("base address 0 = 0x%.8x\n", pD->base0); printf ("base address 1 = 0x%.8x\n", pD->base1); printf ("base address 2 = 0x%.8x\n", pD->base2); printf ("base address 3 = 0x%.8x\n", pD->base3); printf ("base address 4 = 0x%.8x\n", pD->base4); printf ("base address 5 = 0x%.8x\n", pD->base5); printf ("cardBus CIS pointer = 0x%.8x\n", pD->cis); printf ("sub system vendor ID = 0x%.4x\n", (ushort_t)pD->subVendorId); printf ("sub system ID = 0x%.4x\n", (ushort_t)pD->subSystemId); printf ("expansion ROM base address = 0x%.8x\n", pD->romBase); printf ("interrupt line = 0x%.2x\n", (uchar_t)pD->intLine); printf ("interrupt pin = 0x%.2x\n", (uchar_t)pD->intPin); printf ("min Grant = 0x%.2x\n", (uchar_t)pD->minGrant); printf ("max Latency = 0x%.2x\n", (uchar_t)pD->maxLatency); }
STATUS tysHeaderShow
( int busNo, /* bus number */ int deviceNo, /* device number */ int funcNo /* function number */ ) { PCI_HEADER_DEVICE headerDevice; PCI_HEADER_BRIDGE headerBridge; PCI_HEADER_DEVICE * pD = &headerDevice; PCI_HEADER_BRIDGE * pB = &headerBridge;/*
if (pciLibInitStatus != OK) sanity check
return (ERROR);*/
pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE, &pD->headerType); if (pD->headerType & 0x01) /* PCI-to-PCI bridge */ { pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID, &pB->vendorId); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_DEVICE_ID, &pB->deviceId); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_COMMAND, &pB->command); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_STATUS, &pB->status); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_REVISION, &pB->revisionId); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_PROGRAMMING_IF, &pB->progIf); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_SUBCLASS, &pB->subClass); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_CLASS, &pB->classCode); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_CACHE_LINE_SIZE, &pB->cacheLine); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_LATENCY_TIMER, &pB->latency); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE, &pB->headerType); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_BIST, &pB->bist); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_0, &pB->base0); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_1, &pB->base1); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_PRIMARY_BUS, &pB->priBus); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_SECONDARY_BUS, &pB->secBus); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_SUBORDINATE_BUS, &pB->subBus); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_SEC_LATENCY, &pB->secLatency); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_IO_BASE, &pB->ioBase); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_IO_LIMIT, &pB->ioLimit); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_SEC_STATUS, &pB->secStatus); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_MEM_BASE, &pB->memBase); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_MEM_LIMIT, &pB->memLimit); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_PRE_MEM_BASE, &pB->preBase); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_PRE_MEM_LIMIT, &pB->preLimit); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_PRE_MEM_BASE_U, &pB->preBaseUpper); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_PRE_MEM_LIMIT_U, &pB->preLimitUpper); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_IO_BASE_U, &pB->ioBaseUpper); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_IO_LIMIT_U, &pB->ioLimitUpper); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_ROM_BASE, &pB->romBase); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_BRG_INT_LINE, &pB->intLine); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_BRG_INT_PIN, &pB->intPin); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_BRIDGE_CONTROL, &pB->control); tysBheaderPrint (pB);
} else /* PCI device */ { pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_VENDOR_ID, &pD->vendorId); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_DEVICE_ID, &pD->deviceId); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_COMMAND, &pD->command); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_STATUS, &pD->status); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_REVISION, &pD->revisionId); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_PROGRAMMING_IF, &pD->progIf); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_SUBCLASS, &pD->subClass); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_CLASS, &pD->classCode); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_CACHE_LINE_SIZE, &pD->cacheLine); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_LATENCY_TIMER, &pD->latency); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_HEADER_TYPE, &pD->headerType); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_BIST, &pD->bist); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_0, &pD->base0); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_1, &pD->base1); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_2, &pD->base2); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_3, &pD->base3); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_4, &pD->base4); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_5, &pD->base5); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_CIS, &pD->cis); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_SUB_VENDER_ID, &pD->subVendorId); pciConfigInWord (busNo, deviceNo, funcNo, PCI_CFG_SUB_SYSTEM_ID, &pD->subSystemId); pciConfigInLong (busNo, deviceNo, funcNo, PCI_CFG_EXPANSION_ROM, &pD->romBase); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_DEV_INT_LINE, &pD->intLine); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_DEV_INT_PIN, &pD->intPin); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_MIN_GRANT, &pD->minGrant); pciConfigInByte (busNo, deviceNo, funcNo, PCI_CFG_MAX_LATENCY, &pD->maxLatency); tysDheaderPrint (pD);
} return (OK); }
/*******************************************************************************
*
* sysPciSpecialCycle - generate a special cycle with a message
*
* This routine generates a special cycle with a message.
*
* NOMANUAL
*
* RETURNS: OK
*/
STATUS tysPciSpecialCycle
(
int busNo,
UINT32 message
)
{
int deviceNo = 0x0000001f;
int funcNo = 0x00000007;
PCI_OUT_LONG (tyspciConfAddr,
pciConfigBdfPack (busNo, deviceNo, funcNo) |
0x80000000);
PCI_OUT_LONG (tyspciConfData, message);
return (OK);
}
/*******************************************************************************
*
* sysPciConfigRead - read from the PCI configuration space
*
* This routine reads either a byte, word or a long word specified by
* the argument <width>, from the PCI configuration space
* This routine works around a problem in the hardware which hangs
* PCI bus if device no 12 is accessed from the PCI configuration space.
*
* NOMANUAL
*
* RETURNS: OK, or ERROR if this library is not initialized
*/
STATUS tysPciConfigRead
(
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
int width, /* width to be read */
void * pData /* data read from the offset */
)
{
UINT8 retValByte = 0;
UINT16 retValWord = 0;
UINT32 retValLong = 0;
STATUS retStat = ERROR;
if ((busNo == 0) && (deviceNo == 12))
return (ERROR);
switch (width)
{
case 1: /* byte */
PCI_OUT_LONG (tyspciConfAddr,
pciConfigBdfPack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
retValByte = PCI_IN_BYTE (tyspciConfData + (offset & 0x3));
*((UINT8 *)pData) = retValByte;
retStat = OK;
break;
case 2: /* word */
PCI_OUT_LONG (tyspciConfAddr,
pciConfigBdfPack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
retValWord = PCI_IN_WORD (tyspciConfData + (offset & 0x2));
*((UINT16 *)pData) = retValWord;
retStat = OK;
break;
case 4: /* long */
PCI_OUT_LONG (tyspciConfAddr,
pciConfigBdfPack (busNo, deviceNo, funcNo) |
(offset & 0xfc) | 0x80000000);
retValLong = PCI_IN_LONG (tyspciConfData);
*((UINT32 *)pData) = retValLong;
retStat = OK;
break;
default:
retStat = ERROR;
break;
}
return (retStat);
}
/*******************************************************************************
*
* sysPciConfigWrite - write to the PCI configuration space
*
* This routine writes either a byte, word or a long word specified by
* the argument <width>, to the PCI configuration space
* This routine works around a problem in the hardware which hangs
* PCI bus if device no 12 is accessed from the PCI configuration space.
*
* NOMANUAL
*
* RETURNS: OK, or ERROR if this library is not initialized
*/
STATUS tysPciConfigWrite
(
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
int width, /* width to write */
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