sfr SFRNEXT   = 0x85;               /*SFR Page: All */
sfr SFRLAST   = 0x86;               /*SFR Page: All */
sfr SMB0ADR   = 0xC3;               /*SFR Page: 0 SMBusSlave Address */
sfr SMB0CN    = 0xC0;               /*SFR Page: 0 SMBusControl */
sfr SMB0CR    = 0xCF;               /*SFR Page: 0 SMBusClock Rate */
sfr SMB0DAT   = 0xC2;               /*SFR Page: 0 SMBus Data */
sfr SMB0STA   = 0xC1;               /*SFR Page: 0 SMBusStatus */
sfr SP        = 0x81;               /*SFR Page: All */
sfr SPI0CFG   = 0x9A;               /*SFR Page: 0 SPI Configuration */
sfr SPI0CKR   = 0x9D;               /*SFR Page: 0 S I Clock Rate Control */
sfr SPI0CN    = 0xF8;               /*SFR Page: 0 SPI Control */
sfr SPI0DAT   = 0x9B;               /*SFR Page: 0 SPI Data */
sfr SSTA0     = 0x91;               /*SFR Page: 0 UART0 Status and Clock Selection */
sfr TCON      = 0x88;               /*SFR Page: 0 Timer/Counter Control */
sfr TH0       = 0x8C;               /*SFR Page: 0 Timer/Counter 0 High */
sfr TH1       = 0x8D;               /*SFR Page: 0 Timer/Counter 1 High */
sfr TL0       = 0x8A;               /*SFR Page: 0 Timer/Counter 0 Low */
sfr TL1       = 0x8B;               /*SFR Page: 0 Timer/Counter 1 Low */
sfr TMOD      = 0x89;               /*SFR Page: 0 Timer/Counter Mode */
sfr TMR2CF    = 0xC9;               /*SFR Page: 0 Timer/Counter 2 Configuration */
sfr TMR2CN    = 0xC8;               /*SFR Page: 0 Timer/Counter 2 Control */
sfr TMR2H     = 0xCD;               /*SFR Page: 0 Timer/Counter 2 High */
sfr TMR2L     = 0xCC;               /*SFR Page: 0 Timer/Counter 2 Low */
sfr TMR3CF    = 0xC9;               /*SFR Page: 1 Timer/Counter 3 Configuration */
sfr TMR3CN    = 0xC8;               /*SFR Page: 1 Timer 3 Control */
sfr TMR3H     = 0xCD;               /*SFR Page: 1 Timer/Counter 3 High */
sfr TMR3L     = 0xCC;               /*SFR Page: 1 Timer/Counter 3 Low */
sfr TMR4CF    = 0xC9;               /*SFR Page: 2 Timer/Counter 4 Configuration */
sfr TMR4CN    = 0xC8;               /*SFR Page: 2 Timer/Counter 4 Control */
sfr TMR4H     = 0xCD;               /*SFR Page: 2 Timer/Counter 4 High */
sfr TMR4L     = 0xCC;               /*SFR Page: 2 Timer/Counter 4 Low */
sfr WDTCN     = 0xFF;               /*SFR Page: All */
sfr XBR0      = 0xE1;               /*SFR Page: F Port I/O Crossbar Control 0 */
sfr XBR1      = 0xE2;               /*SFR Page: F Port I/O Crossbar Control 1 */
sfr XBR2      = 0xE3;               /*SFR Page: F Port I/O Crossbar Control 2 */
sfr XBR3      = 0xE4;               /*SFR Page: F Port I/O Crossbar Control 3 */

/*  BIT Registers  */

/*  TCON  0x88 */
sbit TF1   = TCON ^ 7;              /* TIMER 1 OVERFLOW FLAG      */
sbit TR1   = TCON ^ 6;              /* TIMER 1 ON/OFF CONTROL     */
sbit TF0   = TCON ^ 5;              /* TIMER 0 OVERFLOW FLAG      */
sbit TR0   = TCON ^ 4;              /* TIMER 0 ON/OFF CONTROL     */
sbit IE1   = TCON ^ 3;              /* EXT. INTERRUPT 1 EDGE FLAG */
sbit IT1   = TCON ^ 2;              /* EXT. INTERRUPT 1 TYPE      */
sbit IE0   = TCON ^ 1;              /* EXT. INTERRUPT 0 EDGE FLAG */
sbit IT0   = TCON ^ 0;              /* EXT. INTERRUPT 0 TYPE      */

/*  SCON0  0x98 */
sbit SM00  = SCON0 ^ 7;             /* SERIAL MODE CONTROL BIT 0           */       
sbit SM10  = SCON0 ^ 6;             /* SERIAL MODE CONTROL BIT 1           */
sbit SM20  = SCON0 ^ 5;             /* MULTIPROCESSOR COMMUNICATION ENABLE */
sbit REN0  = SCON0 ^ 4;             /* RECEIVE ENABLE                      */
sbit TB80  = SCON0 ^ 3;             /* TRANSMIT BIT 8                      */
sbit RB80  = SCON0 ^ 2;             /* RECEIVE BIT 8                       */
sbit TI0   = SCON0 ^ 1;             /* TRANSMIT INTERRUPT FLAG             */
sbit RI0   = SCON0 ^ 0;             /* RECEIVE INTERRUPT FLAG              */

/*  IE  0xA8 */
sbit EA    = IE ^ 7;                /* GLOBAL INTERRUPT ENABLE      */       
sbit ET2   = IE ^ 5;                /* TIMER 2 INTERRUPT ENABLE     */
sbit ES0   = IE ^ 4;                /* SERIAL PORT INTERRUPT ENABLE */
sbit ET1   = IE ^ 3;                /* TIMER 1 INTERRUPT ENABLE     */
sbit EX1   = IE ^ 2;                /* EXTERNAL INTERRUPT 1 ENABLE  */
sbit ET0   = IE ^ 1;                /* TIMER 0 INTERRUPT ENABLE     */
sbit EX0   = IE ^ 0;                /* EXTERNAL INTERRUPT 0 ENABLE  */

/*  IP  0xB8 */
sbit PT2   = IP ^ 5;                /* TIMER 2 PRIORITY                             */     
sbit PS    = IP ^ 4;                /* SERIAL PORT PRIORITY                         */
sbit PT1   = IP ^ 3;                /* TIMER 1 PRIORITY                             */
sbit PX1   = IP ^ 2;                /* EXTERNAL INTERRUPT 1 PRIORITY  */
sbit PT0   = IP ^ 1;                /* TIMER 0 PRIORITY                             */
sbit PX0   = IP ^ 0;                /* EXTERNAL INTERRUPT 0 PRIORITY  */            

/* SMB0CN 0xC0 */
sbit BUSY     =   SMB0CN ^ 7;       /* SMBUS 0 BUSY                    */
sbit ENSMB    =   SMB0CN ^ 6;       /* SMBUS 0 ENABLE                  */
sbit STA      =   SMB0CN ^ 5;       /* SMBUS 0 START FLAG              */
sbit STO      =   SMB0CN ^ 4;       /* SMBUS 0 STOP FLAG               */
sbit SI       =   SMB0CN ^ 3;       /* SMBUS 0 INTERRUPT PENDING FLAG  */
sbit AA       =   SMB0CN ^ 2;       /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
sbit SMBFTE   =   SMB0CN ^ 1;       /* SMBUS 0 FREE TIMER ENABLE       */
sbit SMBTOE   =   SMB0CN ^ 0;       /* SMBUS 0 TIMEOUT ENABLE          */

/*  PSW  */
sbit CY    = PSW ^ 7;               /* CARRY FLAG              */     
sbit AC    = PSW ^ 6;               /* AUXILIARY CARRY FLAG    */
sbit F0    = PSW ^ 5;               /* USER FLAG 0             */
sbit RS1   = PSW ^ 4;               /* REGISTER BANK SELECT 1  */
sbit RS0   = PSW ^ 3;               /* REGISTER BANK SELECT 0  */
sbit OV    = PSW ^ 2;               /* OVERFLOW FLAG           */
sbit F1    = PSW ^ 1;               /* USER FLAG 1             */
sbit P     = PSW ^ 0;               /* ACCUMULATOR PARITY FLAG */

/* PCA0CN D8H */
sbit CF    =   PCA0CN ^ 7;          /* PCA 0 COUNTER OVERFLOW FLAG   */
sbit CR    =   PCA0CN ^ 6;          /* PCA 0 COUNTER RUN CONTROL BIT */
sbit CCF4  =   PCA0CN ^ 4;          /* PCA 0 MODULE 4 INTERRUPT FLAG */
sbit CCF3  =   PCA0CN ^ 3;          /* PCA 0 MODULE 3 INTERRUPT FLAG */
sbit CCF2  =   PCA0CN ^ 2;          /* PCA 0 MODULE 2 INTERRUPT FLAG */
sbit CCF1  =   PCA0CN ^ 1;          /* PCA 0 MODULE 1 INTERRUPT FLAG */
sbit CCF0  =   PCA0CN ^ 0;          /* PCA 0 MODULE 0 INTERRUPT FLAG */

/* ADC0CN E8H */
sbit AD0EN     =   ADC0CN ^ 7;      /* ADC 0 ENABLE                              */
sbit AD0TM     =   ADC0CN ^ 6;      /* ADC 0 TRACK MODE                          */
sbit AD0INT    =   ADC0CN ^ 5;      /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
sbit AD0BUSY   =   ADC0CN ^ 4;      /* ADC 0 BUSY FLAG                           */
sbit AD0CM1    =   ADC0CN ^ 3;      /* ADC 0 START OF CONVERSION MODE BIT 1      */
sbit AD0CM0    =   ADC0CN ^ 2;      /* ADC 0 START OF CONVERSION MODE BIT 0      */
sbit AD0WINT   =   ADC0CN ^ 1;      /* ADC 0 WINDOW COMPARE INTERRUPT FLAG       */
sbit AD0LJST   =   ADC0CN ^ 0;      /* ADC 0 RIGHT JUSTIFY DATA BIT              */

/* SPI0CN F8H */
sbit SPIF     =   SPI0CN ^ 7;       /* SPI 0 INTERRUPT FLAG                  */
sbit WCOL     =   SPI0CN ^ 6;       /* SPI 0 WRITE COLLISION FLAG     */
sbit MODF     =   SPI0CN ^ 5;       /* SPI 0 MODE FAULT FLAG          */
sbit RXOVRN   =   SPI0CN ^ 4;       /* SPI 0 RX OVERRUN FLAG          */
sbit TXBSY    =   SPI0CN ^ 3;       /* SPI 0 TX BUSY FLAG                    */
sbit SLVSEL   =   SPI0CN ^ 2;       /* SPI 0 SLAVE SELECT                    */
sbit MSTEN    =   SPI0CN ^ 1;       /* SPI 0 MASTER ENABLE                   */
sbit SPIEN    =   SPI0CN ^ 0;       /* SPI 0 SPI ENABLE                      */                   

#endif