; define S3C4510b CPU master clock

MHz			EQU		1000000
fMCLK_MHz	EQU		(50 * MHz)
MCLK		EQU		fMCLK_MHz
fMCLK		EQU		(fMCLK_MHz / MHz)
MCLK2		EQU		(fMCLK_MHz / 2)


; ASIC Address Definition

BASE_ADDR	EQU		0x3FF0000


; System Manager Registers
SYSCFG		EQU		(BASE_ADDR+0x0000)
CLKCON		EQU		(BASE_ADDR+0x3000)
EXTACON0	EQU		(BASE_ADDR+0x3008)
EXTACON1	EQU		(BASE_ADDR+0x300C)
EXTDBWTH	EQU		(BASE_ADDR+0x3010)
ROMCON0		EQU		(BASE_ADDR+0x3014)
ROMCON1		EQU		(BASE_ADDR+0x3018)
ROMCON2		EQU		(BASE_ADDR+0x301C)
ROMCON3		EQU		(BASE_ADDR+0x3020)
ROMCON4		EQU		(BASE_ADDR+0x3024)
ROMCON5		EQU		(BASE_ADDR+0x3028)
DRAMCON0	EQU		(BASE_ADDR+0x302C)
DRAMCON1	EQU		(BASE_ADDR+0x3030)
DRAMCON2	EQU		(BASE_ADDR+0x3034)
DRAMCON3	EQU		(BASE_ADDR+0x3038)
REFEXTCON	EQU		(BASE_ADDR+0x303C)


; Ethernet BDMA Registers
BDMATXCON	EQU		(BASE_ADDR+0x9000)
BDMARXCON	EQU		(BASE_ADDR+0x9004)
BDMATXPTR	EQU		(BASE_ADDR+0x9008)
BDMARXPTR	EQU		(BASE_ADDR+0x900C)
BDMARXLSZ	EQU		(BASE_ADDR+0x9010)
BDMASTAT	EQU		(BASE_ADDR+0x9014)
CAMBASE		EQU		(BASE_ADDR+0x9100)

; CAM		0x9100 ~ 0x917C
; BDMATXBUF	0x9200 ~ 0x92FC
; BDMARXBUF	0x9800 ~ 0x99FC

; Ethernet MAC Registers 
MACON		EQU		(BASE_ADDR+0xA000)
CAMCON		EQU		(BASE_ADDR+0xA004)
MACTXCON	EQU		(BASE_ADDR+0xA008)
MACTXSTAT	EQU		(BASE_ADDR+0xA00C)
MACRXCON	EQU		(BASE_ADDR+0xA010)
MACRXSTAT	EQU		(BASE_ADDR+0xA014)
STADATA		EQU		(BASE_ADDR+0xA018)
STACON		EQU		(BASE_ADDR+0xA01C)
CAMEN		EQU		(BASE_ADDR+0xA028)
EMISSCNT	EQU		(BASE_ADDR+0xA03C)
EPZCNT		EQU		(BASE_ADDR+0xA040)
ERMPZCNT	EQU		(BASE_ADDR+0xA044)
EXTSTAT		EQU		(BASE_ADDR+0x9040)

; HDLC Channel A Registers

; HDLC Channel B Registers 



; I/O Ports Registers
IOPMOD		EQU		(BASE_ADDR+0x5000)
IOPCON		EQU		(BASE_ADDR+0x5004)
IOPDATA		EQU		(BASE_ADDR+0x5008)

; Interrupt Controller Registers
INTMOD		EQU		(BASE_ADDR+0x4000)
INTPND		EQU		(BASE_ADDR+0x4004)
INTMSK		EQU		(BASE_ADDR+0x4008)
INTPRI0		EQU		(BASE_ADDR+0x400C)
INTPRI1		EQU		(BASE_ADDR+0x4010)
INTPRI2		EQU		(BASE_ADDR+0x4014)
INTPRI3		EQU		(BASE_ADDR+0x4018)
INTPRI4		EQU		(BASE_ADDR+0x401C)
INTPRI5		EQU		(BASE_ADDR+0x4020)
INTOFFSET	EQU		(BASE_ADDR+0x4024)
INTPNDTST	EQU		(BASE_ADDR+0x402C)
INTOSET_FIQ	EQU		(BASE_ADDR+0x4030)
INTOSET_IRQ	EQU		(BASE_ADDR+0x4034)

INT_MODE_IRQ	EQU		0x000000
INT_MODE_FIQ	EQU		0x1FFFFF
INT_MASK_DIS	EQU		0x1FFFFF
INT_MASK_ENA	EQU		0x000000

; I2C Bus Registers


; GDMA Registers 

; GDMA 0 Registers
GDMACON0	EQU		(BASE_ADDR+0xb000)
GDMASRC0    EQU		(BASE_ADDR+0xb004)
GDMADST0    EQU		(BASE_ADDR+0xb008)
GDMACNT0    EQU		(BASE_ADDR+0xb00c)

; GDMA 1 Registers
GDMACON1    EQU		(BASE_ADDR+0xc000)
GDMASRC1	EQU		(BASE_ADDR+0xc004)
GDMADST1    EQU	    (BASE_ADDR+0xc008)
GDMACNT1    EQU		(BASE_ADDR+0xc00c)

; UART Registers 
ULCON0		EQU		(BASE_ADDR+0xD000)
ULCON1		EQU		(BASE_ADDR+0xE000)
UCON0		EQU		(BASE_ADDR+0xD004)
UCON1		EQU		(BASE_ADDR+0xE004)
USTAT0		EQU		(BASE_ADDR+0xD008)
USTAT1		EQU		(BASE_ADDR+0xE008)
UTXBUF0		EQU		(BASE_ADDR+0xD00C)
UTXBUF1		EQU		(BASE_ADDR+0xE00C)
URXBUF0		EQU		(BASE_ADDR+0xD010)
URXBUF1		EQU		(BASE_ADDR+0xE010)
UBRDIV0		EQU		(BASE_ADDR+0xD014)
UBRDIV1		EQU		(BASE_ADDR+0xE014)

; Timers Registers
TMOD		EQU		(BASE_ADDR+0x6000)
TDATA0		EQU		(BASE_ADDR+0x6004)
TDATA1		EQU		(BASE_ADDR+0x6008)
TCNT0		EQU		(BASE_ADDR+0x600C)
TCNT1		EQU		(BASE_ADDR+0x6010)

; Interrupt
INT_EXTINT0	EQU		0
INT_EXTINT1	EQU		1
INT_EXTINT2	EQU		2
INT_EXTINT3	EQU		3
INT_UARTTX0	EQU		4
INT_UARTRX0	EQU		5
INT_UARTTX1	EQU		6
INT_UARTRX1	EQU		7
INT_GDMA0	EQU		8
INT_GDMA1	EQU		9
INT_TIMER0	EQU		10
INT_TIMER1	EQU		11
INT_HDLCTXA	EQU		12
INT_HDLCRXA	EQU		13
INT_HDLCTXB	EQU		14
INT_HDLCRXB	EQU		15
INT_BDMATX	EQU		16
INT_BDMARX	EQU		17
INT_MACTX	EQU		18
INT_MACRX	EQU		19
INT_IIC		EQU		20
INT_GLOBAL	EQU		21


PSR_MODE_MASK	EQU		0x1f
PSR_USER_MODE   EQU		0x10
PSR_SVC_MODE    EQU		0x13
PSR_IRQ_MODE    EQU		0x12
PSR_FIQ_MODE    EQU		0x11
PSR_UNDEF_MODE  EQU		0x1b
PSR_ABORT_MODE  EQU		0x17
NO_INT			EQU		0xc0

;SYSCFG
CACHE_EN	EQU		2
WRITE_BUF	EQU		4
CACHE_ALL	EQU		0x10
CACHE_HALF	EQU		0
CACHE_OFF	EQU		0x20
SDRAM_ITF	EQU		0x80000000

;ULCON
DATA5b		EQU		0
DATA6b		EQU		1
DATA7b		EQU		2
DATA8b		EQU		3
STOPb1		EQU		0
STOPb2		EQU		4
PARITY_NO	EQU		0
PARITY_O	EQU		0x20
PARITY_E	EQU		0x28
PARITY_1	EQU		0x30
PARITY_0	EQU		0x38
USE_EXT_CLK	EQU		0x40
INFRA_MOD	EQU		0x80

;UCON	
RX_STAT_INT	EQU		4
DSR_SET		EQU		0x20

;USTAT	
DTR_SET		EQU		0x10
RX_READY	EQU		0x20
TX_EMPTY	EQU		0x40
TX_COMPLETE	EQU		0x80

;-------------------------------------------------
	END