/*				24x.cmd command file		*/    
 

MEMORY
{
	PAGE 0:	VECS:	origin=0000h, length=003Fh		/* PROGRAM */
			/*PROG:	origin=0040h, length=00C0h B0 Test */
			PROG:	origin=0040h, length=03000h		/* EMIF */ 

	PAGE 1:	MMRS:	origin=0000h, length=005Fh		/* MMRS */
			B2:		origin=0060h, length=0020h		/* DARAM */
			B0:		origin=0200h, length=0100h		/* DARAM */
			B1:		origin=0300h, length=0100h		/* DARAM */
			DATA:	origin=8000h, length=7fffh		/* EMIF */
}

/*--------------------------------------------------------------------------*/
/* SECTIONS ALLOCATION                                                      */
/*--------------------------------------------------------------------------*/
SECTIONS
{
	.vectors:	{ } > VECS	PAGE 0		/* INTERRUPT VECTOR TABLE     
	.stat:  { } > PROG  PAGE 0     */
	.text:	{ } > PROG	PAGE 0		/* CODE */
	.data:	{ } > PROG	PAGE 0		/* INITIALIZATION DATA TABLES */
	.mmrs:	{ } > MMRS	PAGE 1		/* Memory Mapped Registers */
	.bss:	{ } > DATA	PAGE 1		/* Block B2   */
	.blk0:	{ } > B0	PAGE 1		/* Block B0   */
	.blk1:	{ } > B1	PAGE 1		/* Block B1   */
	.blk2:	{ } > B2	PAGE 1		/* Block B2   */
	.blk3:	{ } > DATA	PAGE 1		/* External Data memory */
}