?? x24x.h
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;**************************************************************************
; File name: X24x.h
; Project: F240 silicon functional test
; Originator: Tianhuang
;
; Description: F240/C240 register definitions.
;__________________________________________________________________________
; Date of Mod | Description
;--------------------------------------------------------------------------
; May. 5, 2003 | Created from header file used by design
;--------------------------------------------------------------------------
; Data memory mapped registers
;--------------------------------------------------------------------------
; C2xx core registers
IMR .set 0004h ; Interrupt Mask register
GREG .set 0005h ; Global memory allocation register
IFR .set 0006h ; Interrupt Flag register
; System configuration and interrupt registers
SYSCR .set 7018h ; System Module Control register
SYSSR .set 701Ah ; System Module Status register
SYSIVR .set 701Eh ; System Interrupt Vector register
; PLL configuration registers
CKCR0 .set 702bh ; PLL Clock Control Register 0
CKCR1 .set 702dh ; PLL Clock Control Register 1
; External interrupt configuration registers
XINT1 .set 7070h ; Interupt 1 Control register
NMI .set 7072h ; Non maskable Interupt Control register
XINT2 .set 7078h ; Interupt 2 Control register
XINT3 .set 707Ah ; Interupt 3Control register
; Digital I/O registers
OCRA .set 7090h ; Output Control register A
OCRB .set 7092h ; Output Control register B
PADATDIR .set 7098h ; I/O port A Data & Direction register
PBDATDIR .set 709Ah ; I/O port B Data & Direction register
PCDATDIR .set 709Ch ; I/O port C Data & Direction register
; Watchdog (WD) registers
WDCNTR .set 7023h ; WD Counter register
WDKEY .set 7025h ; WD Key register
RTICR .set 7027h ; RTI Control register
WDCR .set 7029h ; WD Control register
; ADC registers
ADCTRL1 .set 7032h ; ADC Control register 1
ADCTRL2 .set 7034h ; ADC Control register 2
ADCFIFO1 .set 7036h ; ADC DATA REG FIFO for ADC1
ADCFIFO2 .set 7038h ; ADC DATA REG FIFO for ADC2
; SPI registers
SPICCR .set 7040h ; SPI Configuration Control register
SPICTL .set 7041h ; SPI Operation Control register
SPISTS .set 7042h ; SPI Status register
SPIBRR .set 7044h ; SPI Baud rate control register
SPIEMU .set 7046h ; SPI Emulation buffer register
SPIBUF .set 7047h ; SPI Serial receive buffer register
SPIDAT .set 7049h ; SPI Serial data register
SPIPC1 .set 704Dh ; SPI Port Control register 1
SPIPC2 .set 704Eh ; SPI Port Control register 2
SPIPRI .set 704Fh ; SPI Priority control register
; SCI registers
SCICCR .set 7050h ; SCI Communication control register
SCICTL1 .set 7051h ; SCI Control register 1
SCIHBAUD .set 7052h ; SCI Baud Select register ,high bits
SCILBAUD .set 7053h ; SCI Baud Select register ,low bits
SCICTL2 .set 7054h ; SCI Control register 2
SCIRXST .set 7055h ; SCI Receiver Status register
SCIRXEMU .set 7056h ; SCI Emulation Data Buffer register
SCIRXBUF .set 7057h ; SCI Receiver Data buffer register
SCITXBUF .set 7059h ; SCI Transmit Data buffer register
SCIPC2 .set 705Eh ; SCI Port Control register 2
SCIPRI .set 705Fh ; SCI Priority control register
; Event Manager (EV) registers
GPTCON .set 7400h ; GP Timer control register
T1CNT .set 7401h ; GP Timer 1 counter register
T1CMPR .set 7402h ; GP Timer 1 compare register
T1PR .set 7403h ; GP Timer 1 period register
T1CON .set 7404h ; GP Timer 1 control register
T2CNT .set 7405h ; GP Timer 2 counter register
T2CMPR .set 7406h ; GP Timer 2 compare register
T2PR .set 7407h ; GP Timer 2 period register
T2CON .set 7408h ; GP Timer 2 control register
T3CNT .set 7409h ; GP Timer 3 counter register
T3CMPR .set 740Ah ; GP Timer 3 compare register
T3PR .set 740Bh ; GP Timer 3 period register
T3CON .set 740Ch ; GP Timer 3 control register
;Full &simple compare unit registers-event manger
COMCON .set 7411h ; Compare control register.
ACTR .set 7413h ; Full compare action control register.
SACTR .set 7414h ; Simple compare action control register.
DBTCON .set 7415h ; Dead-band timer control register.
CMPR1 .set 7417h ; Full compare unit compare register 1
CMPR2 .set 7418h ; Full compare unit compare register 2
CMPR3 .set 7419h ; Full compare unit compare register 3
SCMPR1 .set 741Ah ; Single compare unit compare register 1
SCMPR2 .set 741Bh ; Single compare unit compare register 2
SCMPR3 .set 741Ch ; Single compare unit compare register 3
;Capture & Qep Registers-Event Manager
CAPCON .set 7420h ; Capture control register
CAPFIFO .set 7422h ; Capture FIFO status register
CAPFIFO1 .set 7423h ; Capture 1 Two-level deep FIFO register
CAPFIFO2 .set 7424h ; Capture 2 Two-level deep FIFO register
CAPFIFO3 .set 7425h ; Capture 3 Two-level deep FIFO register
CAPFIFO4 .set 7426h ; Capture 4 Two-level deep FIFO register
;Interupt reqisters-Event Manager(EV)
EVIMRA .set 742Ch ; EV Interrupt Mask register A
EVIMRB .set 742Dh ; EV Interrupt Mask register B
EVIMRC .set 742Eh ; EV Interrupt Mask register C
EVIFRA .set 742Fh ; EV Interrupt Flag register A
EVIFRB .set 7430h ; EV Interrupt Flag register B
EVIFRC .set 7431h ; EV Interrupt Flag register C
EVIVRA .set 7432h ; EV Interrupt Vector register A
EVIVRB .set 7433h ; EV Interrupt Vector register B
EVIVRC .set 7434h ; EV Interrupt Vector register C
;--------------------------------------------------------------------------
; Wait State Generator Registers(mapped into I/O space)
;--------------------------------------------------------------------------
WSGR .set 0FFFFh ; Wait-State Generator Control register
;
PORT7 .set 7000h
PORT6 .set 6000h
PORT5 .set 5000h
PORT4 .set 4000h
PORT3 .set 3000h ;rd
PORT2 .set 2000h ;we
PORT1 .set 1000h ;rd
PORT0 .set 0000h ;WE
;;----------------------------------------------------------------------------
; Data Page pointer definition
;----------------------------------------------------------------------------
POINT_PG0 .set 0
POINT_B0 .set 4
DP_PF1 .set 224 ;Page 1 of peripheral file (7000h/80h)
DP_PF2 .set 225 ;IO page
DP_EV .set 232 ;EV Registers Page
;--------------------------------------------------------------------------
; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
;--------------------------------------------------------------------------
BIT15 .set 0000h ; Bit Code for 15
BIT14 .set 0001h ; Bit Code for 14
BIT13 .set 0002h ; Bit Code for 13
BIT12 .set 0003h ; Bit Code for 12
BIT11 .set 0004h ; Bit Code for 11
BIT10 .set 0005h ; Bit Code for 10
BIT9 .set 0006h ; Bit Code for 9
BIT8 .set 0007h ; Bit Code for 8
BIT7 .set 0008h ; Bit Code for 7
BIT6 .set 0009h ; Bit Code for 6
BIT5 .set 000Ah ; Bit Code for 5
BIT4 .set 000Bh ; Bit Code for 4
BIT3 .set 000Ch ; Bit Code for 3
BIT2 .set 000Dh ; Bit Code for 2
BIT1 .set 000Eh ; Bit Code for 1
BIT0 .set 000Fh ; Bit Code for 0
;---------------------------------------------------------------------------
;---------------------------------------------------------------------------
; Bit masks to reset a bit with AND
;---------------------------------------------------------------------------
RSTB15 .set 7FFFh ; Bit Mask for 15
RSTB14 .set 0BFFFh ; Bit Mask for 14
RSTB13 .set 0DFFFh ; Bit Mask for 13
RSTB12 .set 0EFFFh ; Bit Mask for 12
RSTB11 .set 0F7FFh ; Bit Mask for 11
RSTB10 .set 0FBFFh ; Bit Mask for 10
RSTB9 .set 0FDFFh ; Bit Mask for 9
RSTB8 .set 0FEFFh ; Bit Mask for 8
RSTB7 .set 0FF7Fh ; Bit Mask for 7
RSTB6 .set 0FFBFh ; Bit Mask for 6
RSTB5 .set 0FFDFh ; Bit Mask for 5
RSTB4 .set 0FFEFh ; Bit Mask for 4
RSTB3 .set 0FFF7h ; Bit Mask for 3
RSTB2 .set 0FFFBh ; Bit Mask for 2
RSTB1 .set 0FFFDh ; Bit Mask for 1
RSTB0 .set 0FFFEh ; Bit Mask for 0
;---------------------------------------------------------------------------
; Bit masks to set a bit with OR
;---------------------------------------------------------------------------
SETB15 .set 8000h ; Bit Mask for 15
SETB14 .set 4000h ; Bit Mask for 14
SETB13 .set 2000h ; Bit Mask for 13
SETB12 .set 1000h ; Bit Mask for 12
SETB11 .set 0800h ; Bit Mask for 11
SETB10 .set 0400h ; Bit Mask for 10
SETB9 .set 0200h ; Bit Mask for 9
SETB8 .set 0100h ; Bit Mask for 8
SETB7 .set 0080h ; Bit Mask for 7
SETB6 .set 0040h ; Bit Mask for 6
SETB5 .set 0020h ; Bit Mask for 5
SETB4 .set 0010h ; Bit Mask for 4
SETB3 .set 0008h ; Bit Mask for 3
SETB2 .set 0004h ; Bit Mask for 2
SETB1 .set 0002h ; Bit Mask for 1
SETB0 .set 0001h ; Bit Mask for 0
;---------------------------------------------------------------------------
; Macro definitions
;---------------------------------------------------------------------------
KICK_DOG .macro
LDP #0E0H
SPLK #05555h,WDKEY
SPLK #0aaaah,WDKEY
.endm
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