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;/*************************************************************************/
;/* */
;/* FILE NAME VERSION */
;/* */
;/* snds.a SNDS100 Board version 1.0 */
;/* */
;/* COMPONENT */
;/* */
;/* DESCRIPTION */
;/* */
;/* SNDS100 for KS32C5000, KS32C50100 ASSEBLER SYSTEM HEADER FILE */
;/* */
;/* AUTHOR */
;/* */
;/* */
;/* DATA STRUCTURES */
;/* */
;/* */
;/* FUNCTIONS */
;/* */
;/* DEPENDENCIES */
;/* */
;/* */
;/*************************************************************************/
;/*************************************************************************/
;/* Format of the Program Status Register */
;/*************************************************************************/
;/* */
;/* 31 30 29 28 7 6 5 4 3 2 1 0 */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/*| N | Z | C | V | | I | F | T | M4 ~ M0 | */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/* */
;/* Processor Mode and Mask */
;/* */
;/*************************************************************************/
;
FBit EQU &40
IBit EQU &80
LOCKOUT EQU &C0 ;Interrupt lockout value
LOCK_MSK EQU &C0 ;Interrupt lockout mask value
MODE_MASK EQU &1F ;Processor Mode Mask
UDF_MODE EQU &1B ;Undefine Mode(UDF)
ABT_MODE EQU &17 ;Abort Mode(ABT)
SUP_MODE EQU &13 ;Supervisor Mode (SVC)
IRQ_MODE EQU &12 ;Interrupt Mode (IRQ)
FIQ_MODE EQU &11 ;Fast Interrupt Mode (FIQ)
USR_MODE EQU &10 ;User Mode(USR)
;/*************************************************************************/
;/* SYSTEM STACK MEMORY : 8K bytes system stacks are defined at memory.a
;/*************************************************************************/
USR_STACK_SIZE EQU 1024
UDF_STACK_SIZE EQU 512
ABT_STACK_SIZE EQU 512
IRQ_STACK_SIZE EQU 2048
FIQ_STACK_SIZE EQU 2048
SUP_STACK_SIZE EQU 2048
;/*************************************************************************/
;/* SYSTEM USER STACK MEMORY
;/*************************************************************************/
SYSTEM_SIZE EQU 1024 ; Define the system stack size
TIMER_SIZE EQU 1024 ; Define timer HISR stack size
TIMER_PRIORITY EQU 2 ; Timer HISR priority (values from
; 0 to 2, where 0 is highest)
;/*************************************************************************/
;/* SYSTEM CLOCK */
;/*************************************************************************/
MHz EQU 1000000
;#ifdef KS32C50100
fMCLK_MHz EQU 50000000 ; 50MHz, KS32C50100
;#else
;fMCLK_MHz EQU 20000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 25000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 30000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 33000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 40000000 ; 33MHz, KS32C5000
;#endif
fMCLK EQU fMCLK_MHz/MHz
;/*************************************************************************/
;/* SYSTEM MEMORY CONTROL REGISTER EQU TABLES */
;/*************************************************************************/
;
;/* -> EXTDBWTH : Memory Bus Width register */
;-------------------------------------------------------------
;
DSR0 EQU 2:SHL:0 ; ROM0, 0 : Disable
; 1 : Byte
; 2 : Half-Word
; 3 : Word
DSR1 EQU 2:SHL:2 ; ROM1
DSR2 EQU 3:SHL:4 ; ROM2
DSR3 EQU 3:SHL:6 ; ROM3
DSR4 EQU 3:SHL:8 ; ROM4
DSR5 EQU 3:SHL:10 ; ROM5
DSD0 EQU 3:SHL:12 ; DRAM0
DSD1 EQU 3:SHL:14 ; DRAM1
DSD2 EQU 3:SHL:16 ; DRAM2
DSD3 EQU 3:SHL:18 ; DRAM3
DSX0 EQU 3:SHL:20 ; EXTIO0
DSX1 EQU 3:SHL:22 ; EXTIO1
DSX2 EQU 3:SHL:24 ; EXTIO2
DSX3 EQU 3:SHL:26 ; EXTIO3
rEXTDBWTH EQU DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3
;-------------------------------------------------------------
;/* -> ROMCON0 : ROM Bank0 Control register */
;-------------------------------------------------------------
ROMBasePtr0 EQU 0x000:SHL:10 ;=0x0000000
ROMEndPtr0 EQU 0x020:SHL:20 ;=0x0200000
ROMBasePtr0_S EQU 0x100:SHL:10 ;=0x1000000 ;REMAP
ROMEndPtr0_S EQU 0x120:SHL:20 ;=0x1200000
PMC0 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa0 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc0 EQU (0x6:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON0 EQU ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0
rROMCON0_S EQU ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0
;-------------------------------------------------------------
;/* -> ROMCON1 : ROM Bank1 Control register */
;-------------------------------------------------------------
ROMBasePtr1 EQU 0x020:SHL:10 ;=0x0200000
ROMEndPtr1 EQU 0x040:SHL:20 ;=0x0400000
ROMBasePtr1_S EQU 0x120:SHL:10 ;=0x1200000
ROMEndPtr1_S EQU 0x140:SHL:20 ;=0x1400000
PMC1 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa1 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc1 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON1 EQU ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1
rROMCON1_S EQU ROMEndPtr1_S+ROMBasePtr1_S+rTacc1+rTpa1+PMC1
;-------------------------------------------------------------
;/* -> ROMCON2 : ROM Bank2 Control register */
;-------------------------------------------------------------
ROMBasePtr2 EQU 0x040:SHL:10 ;=0x0400000
ROMEndPtr2 EQU 0x060:SHL:20 ;=0x0600000
ROMBasePtr2_S EQU 0x140:SHL:10 ;=0x1400000
ROMEndPtr2_S EQU 0x160:SHL:20 ;=0x1600000
PMC2 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa2 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc2 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON2 EQU ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2
rROMCON2_S EQU ROMEndPtr2_S+ROMBasePtr2_S+rTacc2+rTpa2+PMC2
;-------------------------------------------------------------
;/* -> ROMCON3 : ROM Bank3 Control register */
;-------------------------------------------------------------
ROMBasePtr3 EQU 0x060:SHL:10 ;=0x0600000
ROMEndPtr3 EQU 0x080:SHL:20 ;=0x0800000
ROMBasePtr3_S EQU 0x060:SHL:10 ;=0x1600000
ROMEndPtr3_S EQU 0x080:SHL:20 ;=0x1800000
PMC3 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa3 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc3 EQU (0x2:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON3 EQU ROMEndPtr3+ROMBasePtr3+rTacc3+rTpa3+PMC3
rROMCON3_S EQU ROMEndPtr3_S+ROMBasePtr3_S+rTacc3+rTpa3+PMC3
;-------------------------------------------------------------
;/* -> ROMCON4 : ROM Bank4 Control register */
;-------------------------------------------------------------
ROMBasePtr4 EQU 0x080:SHL:10 ;=0x0800000
ROMEndPtr4 EQU 0x0A0:SHL:20 ;=0x0A00000
ROMBasePtr4_S EQU 0x180:SHL:10 ;=0x1800000
ROMEndPtr4_S EQU 0x1A0:SHL:20 ;=0x1A00000
PMC4 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa4 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc4 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON4 EQU ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4
rROMCON4_S EQU ROMEndPtr4_S+ROMBasePtr4_S+rTacc4+rTpa4+PMC4
;-------------------------------------------------------------
;/* -> ROMCON5 : ROM Bank5 Control register */
;-------------------------------------------------------------
ROMBasePtr5 EQU 0x0A0:SHL:10 ;=0x0A00000
ROMEndPtr5 EQU 0x0C0:SHL:20 ;=0x0C00000
ROMBasePtr5_S EQU 0x1A0:SHL:10 ;=0x1A00000
ROMEndPtr5_S EQU 0x1C0:SHL:20 ;=0x1C00000
PMC5 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa5 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
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