?? init.s
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;/*************************************************************************/
;/* */
;/* FILE NAME VERSION */
;/* */
;/* init.s SNDS100 Board version 1.0 */
;/* */
;/* COMPONENT */
;/* */
;/* */
;/* DESCRIPTION */
;/* */
;/* This file contains the target processor dependent initialization */
;/* routines (boot code) and data. */
;/* */
;/* AUTHOR */
;/* */
;/* */
;/* DATA STRUCTURES */
;/* */
;/* */
;/* FUNCTIONS */
;/* */
;/* */
;/* DEPENDENCIES */
;/* */
;/* snds.a System constants */
;/* */
;/* HISTORY */
;/* */
;/*************************************************************************/
GET memory.a
GET snds.a
AREA Init, CODE, READONLY
; --- Define entry point
EXPORT __main ; defined to ensure that C runtime system
__main ; is not linked in
ENTRY
; --- Setup interrupt / exception vectors
IF :DEF: ROM_AT_ADDRESS_ZERO
; If the ROM is at address 0 this is just a sequence of branches
B Reset_Handler
B Undefined_Handler
B SWI_Handler
B Prefetch_Handler
B Abort_Handler
NOP ; Reserved vector
B IRQ_Handler
B FIQ_Handler
ELSE
; Otherwise we copy a sequence of LDR PC instructions over the vectors
; (Note: We copy LDR PC instructions because branch instructions
; could not simply be copied, the offset in the branch instruction
; would have to be modified so that it branched into ROM. Also, a
; branch instructions might not reach if the ROM is at an address
; > 32M).
MOV R8, #0
ADR R9, Vector_Init_Block
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
; Now fall into the LDR PC, Reset_Addr instruction which will continue
; execution at 'Reset_Handler'
Vector_Init_Block
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD Undefined_Handler
SWI_Addr DCD SWI_Handler
Prefetch_Addr DCD Prefetch_Handler
Abort_Addr DCD Abort_Handler
DCD 0 ; Reserved vector
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
ENDIF
;==========================================================
; The Default Exception Handler Vector Entry Pointer Setup
;==========================================================
FIQ_Handler
SUB sp, sp, #4
STMFD sp!, {r0}
LDR r0, =HandleFiq
LDR r0, [r0]
STR r0, [sp, #4]
LDMFD sp!, {r0, pc}
IRQ_Handler
SUB sp, sp, #4
STMFD sp!, {r0}
LDR r0, =HandleIrq
LDR r0, [r0]
STR r0, [sp, #4]
LDMFD sp!, {r0, pc}
Prefetch_Handler
SUB sp, sp, #4
STMFD sp!, {r0}
LDR r0, =HandlePrefetch
LDR r0, [r0]
STR r0, [sp, #4]
LDMFD sp!, {r0, pc}
Abort_Handler
SUB sp, sp, #4
STMFD sp!, {r0}
LDR r0, =HandleAbort
LDR r0, [r0]
STR r0, [sp, #4]
LDMFD sp!, {r0, pc}
Undefined_Handler
SUB sp, sp, #4
STMFD sp!, {r0}
LDR r0, =HandleUndef
LDR r0, [r0]
STR r0, [sp, #4]
LDMFD sp!, {r0, pc}
SWI_Handler
SUB sp, sp, #4
STMFD sp!, {r0}
LDR r0, =HandleSwi
LDR r0, [r0]
STR r0, [sp, #4]
LDMFD sp!, {r0, pc}
AREA Main, CODE, READONLY
;==========================================================
; The Reset Entry Point
;==========================================================
EXPORT Reset_Handler
Reset_Handler ;/* Reset Entry Point */
LDR r1, =IntMask
LDR r0, =0xFFFFFFFF
STR r0, [r1]
[ ROM_AT_ADDRESS_ZERO
|
LDR r0, =HandleSwi ; SWI exception table address
LDR r1, =SystemSwiHandler
STR r1, [r0]
swi 0xff ;/* Call SWI Vector */
]
;=====================================
; Initialise STACK
;=====================================
INITIALIZE_STACK
MRS r0, cpsr
BIC r0, r0, #LOCKOUT | MODE_MASK
ORR r2, r0, #USR_MODE
ORR r1, r0, #LOCKOUT | FIQ_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =FIQ_STACK
ORR r1, r0, #LOCKOUT | IRQ_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =IRQ_STACK
ORR r1, r0, #LOCKOUT | ABT_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =ABT_STACK
ORR r1, r0, #LOCKOUT | UDF_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =UDF_STACK
ORR r1, r0, #LOCKOUT | SUP_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =SUP_STACK ; Change CPSR to SVC mode
;=====================================
; LED Display
;=====================================
LDR r1, =IOPMODE
LDR r0, =0xFF
STR r0, [r1]
LDR r1, =IOPDATA
LDR r0, =0x55
STR r0, [r1]
;=====================================
; Setup Special Register
;=====================================
LDR r0, =0x3FF0000 ; Read SYSCFG register value
LDR r1,[r0] ; To idetify DRAM type
LDR r2, =0x80000000
AND r0, r1, r2 ; Mask DRAM type mode bit
CMP r0, r2
BNE EDO_DRAM_CONFIGURATION
B SYNC_DRAM_CONFIGURATION ; only when KS32C50100
;==================================================
; Special Register Configuration for EDO mode DRAM
;==================================================
EDO_DRAM_CONFIGURATION
LDR r0, =0x3FF0000
LDR r1, =0x3FFFF90 ; SetValue = 0x3FFFF91
STR r1, [r0] ; Cache,WB disable
; Start_addr = 0x3FF00000
;ROM and RAM Configuration(Multiple Load and Store)
;ADRL r0, SystemInitData
LDR r0, =SystemInitData
LDMIA r0, {r1-r12}
LDR r0, =0x3FF0000 + 0x3010 ; ROMCntr Offset : 0x3010
STMIA r0, {r1-r12}
LDR r1,=DRAM_BASE
STR r1,[r1] ; [DRAM_BASE] = DRAM_BASE
LDR r2,[r1] ; Read DRAM Data
CMP r2,r1
BEQ EXCEPTION_VECTOR_TABLE_SETUP
;==================================================
; Special Register Configuration for SYNC DRAM
;==================================================
SYNC_DRAM_CONFIGURATION
LDR r0, =0x3FF0000
LDR r1, =0x83FFFF90 ; SetValue = 0x83FFFF91
STR r1, [r0] ; Cache,WB disable
; Start_addr = 0x3FF00000
;ROM and RAM Configuration(Multiple Load and Store)
;ADRL r0, SystemInitDataSDRAM
LDR r0, =SystemInitDataSDRAM
LDMIA r0, {r1-r12}
LDR r0, =0x3FF0000 + 0x3010 ; ROMCntr Offset : 0x3010
STMIA r0, {r1-r12}
;=============================
; Exception Vector Table Setup
;=============================
EXCEPTION_VECTOR_TABLE_SETUP
LDR r0, =HandleReset ; Exception Vector Table Memory Loc.
LDR r1, =ExceptionHandlerTable ; Exception Handler Assign
MOV r2, #8 ; Number of Exception is 8
ExceptLoop
LDR r3, [r1], #4
STR r3, [r0], #4
SUBS r2, r2, #1 ; Down Count
BNE ExceptLoop
;=====================================
; Initialise memory required by C code
;=====================================
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different
BEQ %1
0 CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4
STRCC r2, [r1], #4
BCC %0
1 LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
2 CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %2
;====================================================
; Now change to user mode and set up user mode stack.
;====================================================
MRS r0, cpsr
BIC r0, r0, #LOCKOUT | MODE_MASK
ORR r1, r0, #USR_MODE
MSR cpsr_cf, r0
LDR sp, =USR_STACK
; /* Call C_Entry application routine with a pointer to the first */
; /* available memory address after ther compiler's global data */
; /* This memory may be used by the application. */
;===========================
; Now we enter the C Program
;===========================
IMPORT C_Entry
BL C_Entry
;===========================================
; Exception Vector Function Definition
; Consist of function Call from C-Program.
;===========================================
SystemUndefinedHandler
IMPORT ISR_UndefHandler
STMFD sp!, {r0-r12}
B ISR_UndefHandler
LDMFD sp!, {r0-r12, pc}^
SystemSwiHandler
STMFD sp!, {r0-r12,lr}
LDR r0, [lr, #-4]
BIC r0, r0, #0xff000000
CMP r0, #0xff
BEQ MakeSVC
LDMFD sp!, {r0-r12, pc}^
MakeSVC
MRS r1, spsr
BIC r1, r1, #MODE_MASK
ORR r2, r1, #SUP_MODE
MSR spsr_cf, r2
LDMFD sp!, {r0-r12, pc}^
SystemPrefetchHandler
IMPORT ISR_PrefetchHandler
STMFD sp!, {r0-r12, lr}
B ISR_PrefetchHandler
LDMFD sp!, {r0-r12, lr}
;ADD sp, sp, #4
SUBS pc, lr, #4
SystemAbortHandler
IMPORT ISR_AbortHandler
STMFD sp!, {r0-r12, lr}
B ISR_AbortHandler
LDMFD sp!, {r0-r12, lr}
;ADD sp, sp, #4
SUBS pc, lr, #8
SystemReserv
SUBS pc, lr, #4
SystemIrqHandler
IMPORT ISR_IrqHandler
STMFD sp!, {r0-r12, lr}
BL ISR_IrqHandler
LDMFD sp!, {r0-r12, lr}
SUBS pc, lr, #4
SystemFiqHandler
IMPORT ISR_FiqHandler
STMFD sp!, {r0-r7, lr}
BL ISR_FiqHandler
LDMFD sp!, {r0-r7, lr}
SUBS pc, lr, #4
AREA ROMDATA, DATA, READONLY
;======================================================
; DRAM System Initialize Data KS32C50100
;======================================================
SystemInitData
DCD rEXTDBWTH ; DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit
DCD rROMCON0 ; 0x0000000 ~ 0x01FFFFF, ROM0,4Mbit,2cycle
DCD rROMCON1 ;
DCD rROMCON2 ; 0x0400000 ~ 0x05FFFFF, ROM2
DCD rROMCON3 ; 0x0600000 ~ 0x07FFFFF, ROM3
DCD rROMCON4 ; 0x0800000 ~ 0x09FFFFF, ROM4
DCD rROMCON5 ;
DCD rDRAMCON0 ; 0x1000000 ~ 0x13FFFFF, DRAM0 4M,
DCD rDRAMCON1 ; 0x1400000 ~ 0x17FFFFF, DRAM1 4M,
DCD rDRAMCON2 ; 0x1800000 ~ 0x1EFFFFF, DRAM2 16M
DCD rDRAMCON3 ; 0x1C00000 ~ 0x1FFFFFF
DCD rREFEXTCON ; External I/O, Refresh
;======================================================
; SDRAM System Initialize Data (KS32C50100 only)
;======================================================
SystemInitDataSDRAM
DCD rEXTDBWTH ; DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit
DCD rROMCON0 ; 0x0000000 ~ 0x01FFFFF, ROM0,4Mbit,2cycle
DCD rROMCON1 ;
DCD rROMCON2 ; 0x0400000 ~ 0x05FFFFF, ROM2
DCD rROMCON3 ; 0x0600000 ~ 0x07FFFFF, ROM3
DCD rROMCON4 ; 0x0800000 ~ 0x09FFFFF, ROM4
DCD rROMCON5 ;
DCD rSDRAMCON0 ; 0x1000000 ~ 0x13FFFFF, DRAM0 4M,
DCD rSDRAMCON1 ; 0x1400000 ~ 0x17FFFFF, DRAM1 4M,
DCD rSDRAMCON2 ; 0x1800000 ~ 0x1EFFFFF, DRAM2 16M
DCD rSDRAMCON3 ; 0x1C00000 ~ 0x1FFFFFF
DCD rSREFEXTCON ; External I/O, Refresh
;===========================================
; Exception Handler Vector Table Entry Point
;===========================================
ExceptionHandlerTable
DCD UserCodeArea
DCD SystemUndefinedHandler
DCD SystemSwiHandler
DCD SystemPrefetchHandler
DCD SystemAbortHandler
DCD SystemReserv
DCD SystemIrqHandler
DCD SystemFiqHandler
ALIGN
;/***************************************************/
AREA SYS_STACK, NOINIT
;/***************************************************/
% USR_STACK_SIZE
USR_STACK
% UDF_STACK_SIZE
UDF_STACK
% ABT_STACK_SIZE
ABT_STACK
% IRQ_STACK_SIZE
IRQ_STACK
% FIQ_STACK_SIZE
FIQ_STACK
% SUP_STACK_SIZE
SUP_STACK
;/***************************************************/
END
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