// Selected Function
	while(1) {
		switch(ch) {
		case 'U' : // P5 :Count up 
			if (SelCount == 0) SelCount = MAXTESTITEM ; 
			else SelCount-- ; 
			break; 
		case 'D' : // P6 Count down
			if (SelCount < MAXTESTITEM) SelCount++ ; 
			else SelCount = 0  ; 
			break; 
		case 'S' : // P7
			if (SelCount < MAXTESTITEM)
				{
				SelTestItemFunc[SelCount]() ; 
				// Should be attached get_key()
				lPrint("Press Any Key ...") ;
				//ch = get_key() ;
				LCDInit() ;
				continue ;
				}
			else return ; 
		default : break ;
		}
		break ;

	} // End of While : Select Function

	} // End of While : Main Routine
}

// Initialize Test Item Selection Function
void InitTestItemSelFunction(int nItem , void (*TestItem)())
{
    	SelTestItemFunc[nItem] = TestItem;
}

void MemTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("Memory Test ..") ;
	MemoryPartTest() ; 
	lPrint(" Finished.") ;
}

void CacheTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("Cache Test ..") ;
	CacheTest() ; 
	lPrint(" Finished.") ;
}
void IntTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("Interrupt Test ..") ;
	Print("\n Next Version Supported") ;
	//InterruptTest() ; 
	lPrint(" Finished.") ;
}

void DmaTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("DMA Test ..") ;
	GdmaTest() ; 
	lPrint(" Finished.") ;
}

void TimerTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("Timer Test ..") ;
	TimerTest() ; 
	lPrint(" Finished.") ;
}

void MacTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("MAC Test ..") ;
	MacTest() ; 
	lPrint(" Finished.") ;
}

void HdlcTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("HDLC Test ..") ;
	HdlcTest() ; 
	lPrint(" Finished.") ;
}

void I2CTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("I2C Test ..") ;
	//Print("\n Next Version Supported") ;
	IICTest() ; 
	lPrint(" Finished.") ;
}

void UartTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("UART Test ..") ;
	UartTest() ; 
	lPrint(" Finished.") ;
}


void IoFuncDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("I/O Port & share function Test ..") ;
	ioptest(); 
	lPrint(" Finished.") ;
}


void EtcTestDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("ETC Test ..") ;
	//Print("\n Next Version Supported") ;
	EtcTest() ;
	lPrint(" Finished.") ;
}

void AllTestDiag(void)
{
     char * s;

        l2Print("-NetMCU SNDS100-","Test Start..");

	/* TIMER 1 Initialized for mesuring the test time */
	tmReset(TIMER_DEV0);
	tm_init(TIMER_DEV0,(ONE_SECOND/TICKS_PER_SECOND));
	TimerStart(TIMER_DEV0);

	AllTestInternal(1) ;

	TimerStop(TIMER_DEV0);

        s = GetSysTime(TIMER_DEV0);

	if  (AllTestResult != 0 ) 
		{
		Print("\n $$$ All Test Failed !!!!!") ;
		Print("\n $$$ Error Occured Count : %d ", AllTestResult) ;
                l2Print("All Test FAIL!",s); 
		IOPDATA = 0x0f;
		lPrint(" Fail ?") ;
		}
	else
		{
		Print("\n $$$ All Test Passed !!!!!") ;
                l2Print("All Test PASS!",s); 
		IOPDATA = 0xaa ;
		}

	AllTestResult = 0 ;

	Print("\r-------------------------------------------------\r");
	PrtSysTime(TIMER_DEV0,"Total test time"); 
	Print("\r-------------------------------------------------\r");
	ClrTimeVar(TIMER_DEV0);
}

void DownloadDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("Downloading ..") ;
	DownLoadPgm() ; 
	lPrint(" Finished.") ;
}

void FusingDiag(void)
{
	LcdUsrModeSet() ;
	lPrint("Fusing ..") ;
	FlashDown() ; 
	lPrint(" Finished.") ;
}

void BenchMarkDiag(void)
{
	LcdUsrModeSet() ;
	l2Print("KS32C50100 SNDS100","Bench Marking test..") ;

      /* Timer0 used to measure the Dhryston performance */
        //TDATA0 = 0
        //TCNT0 = 0xffffffff;

	Dhrystone() ;
}

// Configuration View
void SysConfig(void)
{
	void *RO_Base 	= Image$$RO$$Base ;
	void *RO_End 	= Image$$RO$$Limit ;
	void *RW_Base 	= Image$$RW$$Base ;
	void *RW_End 	= Image$$RW$$Limit ;

	int *RO_BaseAddr, *RO_EndAddr, RO_Size ;
	int *RW_BaseAddr, *RW_EndAddr, RW_Size ;

	//int *ROM_
	LcdUsrModeSet() ;
	lPrint("System Configuration View ..") ;

	GetSizeOfRom() ;

	RO_BaseAddr = (int *)RO_Base ;
	RO_EndAddr = (int *)RO_End ;
	RO_Size = RO_EndAddr - RO_BaseAddr ;

	RW_BaseAddr = (int *)RW_Base ;
	RW_EndAddr = (int *)RW_End ;
	RW_Size = RW_EndAddr - RW_BaseAddr ;

        //CacheConfig(); // Cache & SRAM control stauts

	Print("\r===============================") ;
	Print("\r>> System Manager Status") ;
	Print("\r===============================") ;
	if (SPSTR & STALL_ENABLE) Print("\r   - Stall Enabled") ;
	else Print("\r   - Stall Disabled") ;

	if (SPSTR & CACHE_ENABLE) Print("\r   - Cache Enabled") ;
	else Print("\r   - Cache Disabled") ;

	if ((SPSTR & SRAM_CACHE) == 0x00 ) 
			Print("\r%6c4K SRAM, 4K CACHE",' ') ;
	else if ((SPSTR & SRAM_CACHE) == 0x10 ) 
			Print("\r%6c0K SRAM, 8K CACHE",' ') ;
	else if ((SPSTR & SRAM_CACHE) == 0x20 ) 
			Print("\r%6c8K SRAM, 0K CACHE",' ') ;
	else Print("\r%6cSRAM/CACHE Status : %x ",' ',(SPSTR & SRAM_CACHE) ) ; 

	if (SPSTR & WRITE_BUF_EN) Print("\r   - Write Buffer Enabled") ;
	else Print("\r   - Write Buffer Disabled") ;

	Print("\r   - SRAM Base Addr  : %8x",((SPSTR & 0xFFC0) << 10) ) ;
	Print("\r===============================") ;

	Print("\r>> Read Only Memory Used") ;
	Print("\r===============================") ;
	Print("\r   - Read Only Base  : %8x",RO_BaseAddr) ;
	Print("\r   - Read Only End   : %8x",RO_EndAddr) ;
	Print("\r   - Read Only Size  : %8d",RO_Size) ;
	Print("\r===============================") ;
	Print("\r>> Read/Write Memory Used") ;
	Print("\r===============================") ;
	Print("\r   - Read/Write Base : %8x",RW_BaseAddr) ;
	Print("\r   - Read/Write End  : %8x",RW_EndAddr) ;
	Print("\r   - Read/Write Size : %8d",RW_Size) ;
	Print("\r===============================") ;

}


void GetSizeOfRom(void)
{
	Print("\r===============================") ;
	Print("\r>> EEPROM Data Bus Size is ") ;
	if ( (EXTDBWTH & 0x3) == B0SIZE_BYTE ) 
			Print("BYTE") ;
	else if ( (EXTDBWTH & 0x3) == B0SIZE_SHORT ) 
			Print("SHORT") ;
	else if ( (EXTDBWTH & 0x3) == B0SIZE_WORD ) 
			Print("WORD") ;
}


void EtcTest0(void) 
{
	U32 *RomBase1, *DramBase1, *ExtIoBase2 ;
	Print("\n >> Etc Test <<") ;

	RomBase1 = (U32 *)ROMBasePtr1 ;
	DramBase1 = (U32 *)DRAMBasePtr1 ;
	ExtIoBase2 = (U32 *)EXTIOBasePtr2 ;

	Print("\n +- External Bank2 Read/Write : Press Any Key to Exit\r") ;
	Print("\r EXTACON1 : %x",EXTACON1) ;
	EXTACON1 = ETCOS2 | ETACS2 | ETCOH2 | ETACC2 ; 
	Print("\r EXTACON1 : %x\r",EXTACON1) ;

	do {
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
		*ExtIoBase2= *(ExtIoBase2+1) ;
	}while( !kbd_hit() ) ;

	Print("\n +- ROM Bank1 Read/Write : Press Any Key to Exit\r") ;
	do {
		*RomBase1 = *(RomBase1+1) ;
	}while( !kbd_hit() ) ;

	Print("\r DRAMCON0 : %x, DRAMCON1 : %x",DRAMCON0,DRAMCON1) ;
	Print("\r REFEXTCON : %x",REFEXTCON) ;
	Print("\n +- DRAM Bank1 Read/Write : Press Any Key to Exit\r") ;
	do {
		*DramBase1 = *(DramBase1+1) ;
	}while( !kbd_hit() ) ;

	Print("\n +- I/O Port 8 Write 1 ") ;
	IOPMOD = 0xF1F ;
	do {
		IOPDATA = 0xFF0 ;
	}while( !kbd_hit() ) ;

	Print("\n +- I/O Port 8 Write 0 ") ;
	do {
		IOPDATA = 0x001 ;
		IOPDATA = 0xF02 ;
		IOPDATA = 0x001 ;
		IOPDATA = 0xF02 ;
		IOPDATA = 0x001 ;
		IOPDATA = 0xF02 ;
		IOPDATA = 0x001 ;
		IOPDATA = 0xF02 ;
	}while( !kbd_hit() ) ;

}