?? norom.s
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GET memory.a
;; GET snds.a
GET newsnds.a
AREA Init, CODE, READONLY
; --- Define entry point
EXPORT __main ; defined to ensure that C runtime system
__main ; is not linked in
ENTRY
; --- Setup interrupt / exception vectors
; then we copy a sequence of LDR PC instructions over the vectors
; (Note: We copy LDR PC instructions because branch instructions
; could not simply be copied, the offset in the branch instruction
; would have to be modified so that it branched into ROM. Also, a
; branch instructions might not reach if the ROM is at an address
; > 32M).
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV R8, #0
ADR R9, Vector_Init_Block
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
; Now fall into the LDR PC, Reset_Addr instruction which will continue
; execution at 'Reset_Handler'
Vector_Init_Block
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD SystemUndefinedHandler
SWI_Addr DCD SystemSwiHandler
Prefetch_Addr DCD SystemPrefetchHandler
Abort_Addr DCD SystemAbortHandler
DCD 0 ; Reserved vector
IRQ_Addr DCD SystemIrqHandler
FIQ_Addr DCD SystemFiqHandler
AREA Main, CODE, READONLY
;==========================================================
; The Reset Entry Point
;==========================================================
EXPORT Reset_Handler
Reset_Handler ;/* Reset Entry Point */
LDR r1, =IntMask
LDR r0, =0xFFFFFFFF
STR r0, [r1]
;=====================================
; Initialise STACK
;=====================================
INITIALIZE_STACK
MRS r0, cpsr
BIC r0, r0, #LOCKOUT | MODE_MASK
ORR r2, r0, #USR_MODE
ORR r1, r0, #LOCKOUT | FIQ_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =FIQ_STACK
ORR r1, r0, #LOCKOUT | IRQ_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =IRQ_STACK
ORR r1, r0, #LOCKOUT | ABT_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =ABT_STACK
ORR r1, r0, #LOCKOUT | UDF_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =UDF_STACK
ORR r1, r0, #LOCKOUT | SUP_MODE
MSR cpsr_cf, r1
MSR spsr_cf, r2
LDR sp, =SUP_STACK ; Change CPSR to SVC mode
;=====================================
; LED Display
;=====================================
LDR r1, =IOPMOD
LDR r0, =0xFF
STR r0, [r1]
LDR r1, =IOPDATA
LDR r0, =0x55
STR r0, [r1]
;=====================================
; Initialise memory required by C code
;=====================================
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different
BEQ %1
0 CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4
STRCC r2, [r1], #4
BCC %0
1 LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
2 CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %2
;====================================================
; Now change to user mode and set up user mode stack.
;====================================================
MRS r0, cpsr
BIC r0, r0, #LOCKOUT | MODE_MASK
ORR r1, r0, #USR_MODE
MSR cpsr_cf, r0
LDR sp, =USR_STACK
; /* Call C_Entry application routine with a pointer to the first */
; /* available memory address after ther compiler's global data */
; /* This memory may be used by the application. */
;===========================
; Now we enter the C Program
;===========================
IMPORT C_Entry
BL C_Entry
;===========================================
; Exception Vector Function Definition
; Consist of function Call from C-Program.
;===========================================
SystemUndefinedHandler
IMPORT ISR_UndefHandler
STMFD sp!, {r0-r12}
B ISR_UndefHandler
LDMFD sp!, {r0-r12, pc}^
SystemSwiHandler
STMFD sp!, {r0-r12,lr}
LDR r0, [lr, #-4]
BIC r0, r0, #0xff000000
CMP r0, #0xff
BEQ MakeSVC
CMP r0, #0xf0
BEQ SDRAMInit
LDMFD sp!, {r0-r12, pc}^
MakeSVC
MRS r1, spsr
BIC r1, r1, #MODE_MASK
ORR r2, r1, #SUP_MODE
MSR spsr_cf, r2
LDMFD sp!, {r0-r12, pc}^
SDRAMInit
LDR r0, =SystemInitDataSDRAM_S
LDMIA r0, {r1-r12}
LDR r0, =0x3FF0000 + 0x3010 ;ROMCntr Offset : 0x3010
STMIA r0, {r1-r12}
MOV pc,lr
SystemPrefetchHandler
IMPORT ISR_PrefetchHandler
STMFD sp!, {r0-r12, lr}
B ISR_PrefetchHandler
LDMFD sp!, {r0-r12, lr}
;ADD sp, sp, #4
SUBS pc, lr, #4
SystemAbortHandler
IMPORT ISR_AbortHandler
STMFD sp!, {r0-r12, lr}
B ISR_AbortHandler
LDMFD sp!, {r0-r12, lr}
;ADD sp, sp, #4
SUBS pc, lr, #8
SystemReserv
SystemIrqHandler
IMPORT ISR_IrqHandler
STMFD sp!, {r0-r12, lr}
BL ISR_IrqHandler
LDMFD sp!, {r0-r12, lr}
SUBS pc, lr, #4
SystemFiqHandler
IMPORT ISR_FiqHandler
STMFD sp!, {r0-r7, lr}
BL ISR_FiqHandler
LDMFD sp!, {r0-r7, lr}
SUBS pc, lr, #4
ALIGN
AREA ROMDATA, DATA, READONLY
;======================================================
; DRAM System Initialize Data(KS32C5000 and KS32C50100)
;======================================================
SystemInitData
DCD rEXTDBWTH ; DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit
DCD rROMCON0 ; 0x0000000 ~ 0x01FFFFF, ROM0,4Mbit,2cycle
DCD rROMCON1 ;
DCD rROMCON2 ; 0x0400000 ~ 0x05FFFFF, ROM2
DCD rROMCON3 ; 0x0600000 ~ 0x07FFFFF, ROM3
DCD rROMCON4 ; 0x0800000 ~ 0x09FFFFF, ROM4
DCD rROMCON5 ;
DCD rDRAMCON0 ; 0x1000000 ~ 0x13FFFFF, DRAM0 4M,
DCD rDRAMCON1 ; 0x1400000 ~ 0x17FFFFF, DRAM1 4M,
DCD rDRAMCON2 ; 0x1800000 ~ 0x1EFFFFF, DRAM2 16M
DCD rDRAMCON3 ; 0x1C00000 ~ 0x1FFFFFF
DCD rREFEXTCON ; External I/O, Refresh
SystemInitData_S
DCD rEXTDBWTH ; DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit
DCD rROMCON0_S ; 0x1000000 ~ 0x11FFFFF, ROM0,4Mbit,2cycle
DCD rROMCON1_S ; 0x1200000 ~ 0x13FFFFF, ROM0
DCD rROMCON2_S ; 0x1400000 ~ 0x15FFFFF, ROM2
DCD rROMCON3_S ; 0x1600000 ~ 0x17FFFFF, ROM3
DCD rROMCON4_S ; 0x1800000 ~ 0x19FFFFF, ROM4
DCD rROMCON5_S ; 0x1A00000 ~ 0x1BFFFFF, ROM4
DCD rDRAMCON0_S ; 0x0000000 ~ 0x03FFFFF, DRAM0 4M,
DCD rDRAMCON1_S ; 0x0400000 ~ 0x07FFFFF, DRAM1 4M,
DCD rDRAMCON2_S ; 0x0800000 ~ 0x0EFFFFF, DRAM2 16M
DCD rDRAMCON3_S ; 0x0C00000 ~ 0x0FFFFFF
DCD rREFEXTCON ; External I/O, Refresh
;======================================================
; SDRAM System Initialize Data (KS32C50100 only)
;======================================================
SystemInitDataSDRAM
DCD rEXTDBWTH ; DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit
DCD rROMCON0 ; 0x0000000 ~ 0x01FFFFF, ROM0,4Mbit,2cycle
DCD rROMCON1 ;
DCD rROMCON2 ; 0x0400000 ~ 0x05FFFFF, ROM2
DCD rROMCON3 ; 0x0600000 ~ 0x07FFFFF, ROM3
DCD rROMCON4 ; 0x0800000 ~ 0x09FFFFF, ROM4
DCD rROMCON5 ;
DCD rSDRAMCON0 ; 0x1000000 ~ 0x13FFFFF, DRAM0 4M,
DCD rSDRAMCON1 ; 0x1400000 ~ 0x17FFFFF, DRAM1 4M,
DCD rSDRAMCON2 ; 0x1800000 ~ 0x1EFFFFF, DRAM2 16M
DCD rSDRAMCON3 ; 0x1C00000 ~ 0x1FFFFFF
DCD rSREFEXTCON ; External I/O, Refresh
SystemInitDataSDRAM_S
DCD rEXTDBWTH ; DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit
DCD rROMCON0_S ; 0x1000000 ~ 0x11FFFFF, ROM0,4Mbit,2cycle
DCD rROMCON1_S ; 0x1200000 ~ 0x13FFFFF, ROM0
DCD rROMCON2_S ; 0x1400000 ~ 0x15FFFFF, ROM2
DCD rROMCON3_S ; 0x1600000 ~ 0x17FFFFF, ROM3
DCD rROMCON4_S ; 0x1800000 ~ 0x19FFFFF, ROM4
DCD rROMCON5_S ; 0x1A00000 ~ 0x1BFFFFF, ROM4
DCD rSDRAMCON0_S ; 0x0000000 ~ 0x03FFFFF, DRAM0 4M,
DCD rSDRAMCON1_S ; 0x0400000 ~ 0x07FFFFF, DRAM1 4M,
DCD rSDRAMCON2_S ; 0x0800000 ~ 0x0EFFFFF, DRAM2 16M
DCD rSDRAMCON3_S ; 0x0C00000 ~ 0x0FFFFFF
DCD rSREFEXTCON ; External I/O, Refresh
SystemInitDataSDRAM_S2
DCD 0x0aa0300a ; DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit
DCD 0x1204002C ; 0x1000000 ~ 0x11FFFFF, ROM0,4Mbit,2cycle
DCD 0x1605002C ; 0x1200000 ~ 0x13FFFFF, ROM0
DCD 0x16044060 ; 0x1400000 ~ 0x15FFFFF, ROM2
DCD 0x18058060 ; 0x1600000 ~ 0x17FFFFF, ROM3
DCD 0x1a060060 ; 0x1800000 ~ 0x19FFFFF, ROM4
DCD 0x1c068060 ; 0x1A00000 ~ 0x1BFFFFF, ROM4
DCD 0x10000390 ; 0x0000000 ~ 0x03FFFFF, DRAM0 4M,
DCD 0x00000110 ; 0x0400000 ~ 0x07FFFFF, DRAM1 4M,
DCD 0x00000110 ; 0x0800000 ~ 0x0EFFFFF, DRAM2 16M
DCD 0x00000110 ; 0x0C00000 ~ 0x0FFFFFF
DCD 0xffa982fe ; External I/O, Refres
;/***************************************************/
AREA SYS_STACK, NOINIT
;/***************************************************/
% USR_STACK_SIZE
USR_STACK
% UDF_STACK_SIZE
UDF_STACK
% ABT_STACK_SIZE
ABT_STACK
% IRQ_STACK_SIZE
IRQ_STACK
% FIQ_STACK_SIZE
FIQ_STACK
% SUP_STACK_SIZE
SUP_STACK
;/***************************************************/
END
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