?? f51mble3.a51
字號:
; DPL = Address Byte Low *
; (2) Byte Count (in R6) *
; *
; RETURNS: NONE *
; *
; DESTROYED: ACC,B,R0,R1,R2,R3,R6,DPTR *
; *
; This routine receives the Starting Address and Length of Bytes to *
; Write from the main loop. It then writes the data bytes received *
; into selected allocation byte. *
; *
;************************************************************************
program_b:
mov B, #SFCM_PB
mov a, DPH
clr c
subb a, #0f0h
jnc exit3
lcall INBYTE ; fetch a byte from serial port
orl SFCF, #0C0h ; set VIS & IAPEN bits = 1
mov SFAH, DPH ; set address to write
mov SFAL, DPL
mov SFDT, A ; set data
mov SFCM, B ; issue program-byte cmd
mov CMD, #04h ; mask Flash_Busy bit in done?
lcall done? ; wait for command to complete
anl SFCF, #00111111b ; VIS=IAPEN=0
inc DPTR ; point to next byte address to be written
djnz COUNT, program_b ; repeat loop until all data written
exit3: anl SFCF, #00111111b ; VIS=IAPEN=0
mov SFDT, #0 ; any value other than 55h
mov SFAH, #0abh ; point to off-chip memory
mov SFAL, #0cdh
mov B, #0 ; invalid IAP command
ret
;========================================================================
nop
nop
nop
sjmp $ ; software trap
;========================================================================
;************************************************************************
; *
; Name: BURST PROGRAM ROUTINE (IAP CMD: 06h) *
; *
; INPUTS: (1) Starting Address: *
; DPH = Address Byte High *
; DPL = Address Byte Low *
; (2) Byte Count (in R6) *
; *
; RETURNS: final state of flash operation in ACC, also send to PC *
; *
; DESTROYED: ACC,B,R0,R1,R2,R3,R6,DPTR *
; *
; This routine is similar to above program_b, it receives Starting Addr.*
; and Length of Bytes to Write from the main loop, and then writes the *
; bytes got from PC into selected allocation byte with Burst-Program *
; mode. *
;************************************************************************
burst_p:
mov B, #SFCM_BP
mov a, DPH ; can NOT burst-program Block1
clr c
subb a, #0f0h
jnc exit4
lcall INBYTE ; fetch a byte from serial port
orl SFCF, #0C0h ; set VIS & IAPEN bits = 1
mov SFAH, DPH ; set address to write
mov SFAL, DPL
mov SFDT, A ; set data
mov SFCM, B ; issue burst-program cmd
mov CMD, #08h ; mask Busy bit in done? (Not Flash_busy bit!)
lcall done? ; wait for burst-program to complete
anl SFCF, #00111111b ; VIS=IAPEN=0
inc DPTR ; point to next byte address to be written
djnz COUNT, burst_p ; repeat until all data written
mov CMD, #04h ; mask SFST.2 to check Flash_Busy bit
lcall done? ; wait for flash operation to finish
lcall OUTBYTE ; send status to PC
exit4: anl SFCF, #00111111b ; VIS=IAPEN=0
mov SFDT, #0 ; any value other than 55h
mov SFAH, #0abh ; point to off-chip memory
mov SFAL, #0cdh
mov B, #0 ; invalid IAP command
ret
;========================================================================
nop
nop
nop
sjmp $ ; software trap
;========================================================================
;************************************************************************
; *
; Name: VERIFY BYTE ROUTINE (IAP CMD: 0Ch) *
; *
; INPUTS: (1) Starting Address: *
; DPH = Address Byte High *
; DPL = Address Byte Low *
; (2) Sector Byte Length (in R6) *
; *
; RETURNS: ACC and SFDT contains the last byte data to be read *
; *
; DESTROYED: ACC,DPTR,R6 *
; *
; This routine reads the data bytes beginning at the flash memory loca- *
; tion requested, and sends each data byte read immediately to the PC. *
; *
;************************************************************************
verify_b:
mov a, DPH ; can NOT burst-program Block1
clr c
subb a, #0f0h
jc block0
orl SFCF, #80h ; VIS=1
clr a
movc a, @a+dptr ; use movc to read contents in block1
sjmp tellpc
block0: orl SFCF, #0C0h ; set VIS & IAPEN bits = 1
mov SFAH, DPH ; load sfah with high address byte
mov SFAL, DPL ; load sfal with low address byte
mov SFCM, #SFCM_VB ; issue verify byte command
nop
nop
nop
mov a, SFDT
tellpc: lcall OUTBYTE ; send data byte to PC
inc DPTR ; point to next data byte address
djnz COUNT, verify_b ; read next byte until count reaches zero
anl SFCF, #00111111b ; VIS=IAPEN=0
mov SFDT, #0 ; any value other than 55h
mov SFAH, #0abh ; point to off-chip memory
mov SFAL, #0cdh
mov B, #0 ; invalid IAP command
ret
;========================================================================
nop
nop
nop
sjmp $ ; software trap
;========================================================================
;************************************************************************
;* *
;* CHECK WHETHER THE FLASH OPERATION IS COMPLETED *
;* *
;************************************************************************
; *
; INPUT: CMD = 04h to detect SFST.2 ( Flash_Busy ) or *
; = 08h to detect SFST.3 ( Busy ) *
; *
; RETURN: flag ACC.2=1 If Flash operation is still busy after elapse *
; of maximum 3000 cycles (about 3.25ms at 11.0592 MHz cystal). *
; otherwise, flag ACC.2=0 means successful operation *
; *
;************************************************************************
done?: mov r1, #250 ; 250 * (1+1+6+2+2) = 3000 cycles
busy: mov a, SFST ; 1 cycle
anl a, CMD ; 1 cycle
nop ; 6 cycles of nop
nop
nop
nop
nop
nop
jz ready ; 2 cycles
djnz r1, busy ; 2 cycles
mov a, #11000100b ; ACC.2=1 indicates flash timeout error
sjmp status
ready: mov a, #0C0h ; ACC.2=0 means successful operation
status: orl a, r0 ; r0 keeps history of timeout
mov r0, a
ret
;========================================================================
nop
nop
nop
sjmp $ ; software trap
;========================================================================
;************************************************************************
;* *
;* RESETVAL ROUTINE *
;* *
;************************************************************************
;* 1. Turn on / off WDT based on Remapping range. *
;* 2. Restore Reset values into SFRs. *
;* 3. Execute User's Code starting at 0000h in block 0. *
;* *
;************************************************************************
resetval:
mov a, SFCF
anl a, #00000011b ; MASK MAP_EN1 & MAP_EN0
anl WDTC, #00000100b ; clear all other bits except WDTC.2
cjne a, #3, register
orl WDTC, #00001011b ; turn on WDT before exits from BSL1.1E
register:
CLR A
MOV B, A
MOV PSW, A
MOV SP, #07H
MOV DPTR, #0
MOV IE, #40H
MOV IP, A
MOV PCON, A
ANL SFST, #11100000B
MOV SFCM, A
MOV SFDT, A
MOV SFAL, A
MOV SFAH, A
MOV RCAP2L, A
MOV RCAP2H, A
MOV TL2, A
MOV TH2, A
MOV T2CON,A
MOV SCON, A
MOV TCON, A
MOV TMOD, A
MOV TL0, A
MOV TH0, A
MOV TL1, A
MOV TH1, A
mov STR1, #'D' ; destroy data at 08h,09h,0Ah,0Bh in SRAM
mov STR2, #'O'
mov STR3, #'N'
mov STR4, #'E'
orl SFCF, #80h ; VIS=1 !!
anl SFCF, #80h ; VIS=1, IAPEN=0, REMAP=0KB
ljmp 0000h ; jump to user's code at 0000h in block 0
;=====================================================================
nop
nop
nop
sjmp $
END
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