///////////////////////////////////////////////////////////////////////////////
//
//    (C) Copyright 1995 - 1997 OSR Open Systems Resources, Inc.
//    All Rights Reserved
//
//    This sofware is supplied for instructional purposes only.
//
//    OSR Open Systems Resources, Inc. (OSR) expressly disclaims any warranty
//    for this software.  THIS SOFTWARE IS PROVIDED  "AS IS" WITHOUT WARRANTY
//    OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION,
//    THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A PARTICULAR
//    PURPOSE.  THE ENTIRE RISK ARISING FROM THE USE OF THIS SOFTWARE REMAINS
//    WITH YOU.  OSR's entire liability and your exclusive remedy shall not
//    exceed the price paid for this material.  In no event shall OSR or its
//    suppliers be liable for any damages whatsoever (including, without
//    limitation, damages for loss of business profit, business interruption,
//    loss of business information, or any other pecuniary loss) arising out
//    of the use or inability to use this software, even if OSR has been
//    advised of the possibility of such damages.  Because some states/
//    jurisdictions do not allow the exclusion or limitation of liability for
//    consequential or incidental damages, the above limitation may not apply
//    to you.
//
//    OSR Open Systems Resources, Inc.
//    105 Route 101A Suite 19
//    Amherst, NH 03031  (603) 595-6500 FAX: (603) 595-6503
//    email bugs to: bugs@osr.com
//
//
//    MODULE:
//
//        ISR_DPC.C
//
//    ABSTRACT:
//
//      This file contains the ISR and DPC for the OSR Sample
//      PCI Busmaster DMA device driver for the AMCC 5933 chip.
//
//    AUTHOR(S):
//
//        OSR Open Systems Resources, Inc.
// 
//    REVISION:   
//
//
///////////////////////////////////////////////////////////////////////////////

#include "osr-pci.h"

///////////////////////////////////////////////////////////////////////////////
//
//  OsrHandleInterrupt
//
//      When the AMCC device generates an interrupt, this function is called.
//      Note that in our simple model of the world here, every transfer is
//      completed successfully.  We just don't bother with error detection
//      and handling.  If you wanted this to be a REAL driver, you'd have to
//      do the appropriate error detection and handling.
//
//  INPUTS:
//
//      Interupt - Address of the KINTERRUPT Object for our device.
//  
//      ServiceContext - Address of our device extension.
//
//  OUTPUTS:
//
//      None.
//
//  RETURNS:
//
//      TRUE if our device is interrupting, FALSE otherwise.
//
//  IRQL:
//
//      This routine is called at IRQL == DIRQL.
//
//  NOTES:
//
//      As is true for all ISR's in NT, this routine is called with the
//      interrupt spin lock held.
//
///////////////////////////////////////////////////////////////////////////////
BOOLEAN OsrHandleInterrupt(PKINTERRUPT Interupt, PVOID ServiceContext)
{
    BOOLEAN ourDeviceInterrupting = FALSE;
    POSR_DEVICE_EXT devExt = (POSR_DEVICE_EXT)ServiceContext;
    ULONG intRegister;
    ULONG csrRegister;

#if DBG
    DbgPrint("OSRPCI: ISR entered\n");
#endif    
    
    //
    // Get the current interrupt CSR from our device
    //
    intRegister = READ_PORT_ULONG(devExt->AmccBaseRegisterAddress+ICSR_OFF);

#if DBG
    DbgPrint("*****************AMCC INTCSR = 0x%0x\n",intRegister);
    OsrPrintIntcsr(intRegister);
#endif


    //
    // Is our device presently interrupting?
    //
    if (intRegister & AMCC_INT_INTERRUPTED) {
    
        //
        // Yes, it is!
        //
        ourDeviceInterrupting = TRUE;

#if DBG
        DbgPrint("\tInterrupt is ours.\n");
#endif

        //
        // Store away some context so when we get to our DpcForIsr we'll know
        // what caused the interrupt.  Specifically, we accumulate bits in the
        // "IntCsr" field of our device extenstion indicating what interrupts
        // we've seen from the device.  Note that since we support simultaneous
        // read and write DMA operations, we could get both a read complete
        // interrupt and a write complete interrupt before the DpcForIsr has
        // had a chance to execute.  Thus, we must carefully ACCUMULATE the
        // bits.
        //
        // N.B.  We guard these bits with the Interrupt Spin Lock.  The bits
        //       cannot be set or cleared unless holding that lock.
        //
        devExt->IntCsr |= (intRegister & AMCC_INT_ACK_BITS);
                        
        //
        // Acknowledge the interrupt on the device
        //
        WRITE_PORT_ULONG(devExt->AmccBaseRegisterAddress+ICSR_OFF, intRegister);

        //
        // IF the interrupt was as a result of a READ or WRITE operation
        // completing (either with success or error) request our DpcForIsr.
        //
        if(intRegister & (AMCC_INT_READ_COMP | AMCC_INT_WRITE_COMP))  {

#if DBG
            DbgPrint("Requesting DPC\n");
#endif
            IoRequestDpc(devExt->DeviceObject, 0, NULL);
        }
        
    }

    return(ourDeviceInterrupting);
}
    


//
// Synchronize Functions
//

///////////////////////////////////////////////////////////////////////////////
//
//  ReadIsDone
//
//    This is a synchronize function, called with the ISR spinlock held, that 
//    checks and potentially updates the READ COMPLETE bit in the IntCsr copy
//    that we keep in our device extension.  These bits must be updated under
//    lock.
//
//  INPUTS:
//
//    ServiceContext - Address of our device extension.
//
//  OUTPUTS:
//
//      None.
//
//  RETURNS:
//
//      TRUE, if a read is complete, FALSE otherwise.
//
//  IRQL:
//
//      This routine is called at IRQL == DIRQL, specifically the Synchronize
//      IRQL for the device.
//
//  NOTES:
//
//      Remember: A read operation to us is actually called a WRITE operation
//                on the AMCC device.  Ugh.  HARDWARE people!
//
///////////////////////////////////////////////////////////////////////////////
BOOLEAN
ReadIsDone(IN PVOID SynchronizeContext)
{
    POSR_DEVICE_EXT devExt = (POSR_DEVICE_EXT)SynchronizeContext;

    //
    // Is a READ operation complete on the device?
    // (Yes, the correct bit to check is _WRITE_COMP!)
    //
    if(devExt->IntCsr & AMCC_INT_WRITE_COMP)  {

        devExt->IntCsr &=  ~AMCC_INT_WRITE_COMP;

        return(TRUE);
    }
        
   return(FALSE);
}    


///////////////////////////////////////////////////////////////////////////////
//
//  WriteIsDone
//
//    This is a synchronize function, called with the ISR spinlock held, that 
//    checks and potentially updates the WRITE COMPLETE bit in the IntCsr copy
//    that we keep in our device extension.  These bits must be updated under
//    lock.
//
//  INPUTS:
//
//    ServiceContext - Address of our device extension.
//
//  OUTPUTS:
//
//      None.
//
//  RETURNS:
//
//      TRUE, if a write is complete, FALSE otherwise.
//
//  IRQL:
//
//      This routine is called at IRQL == DIRQL, specifically the Synchronize
//      IRQL for the device.
//
//  NOTES:
//
//      Remember: A write operation to us is actually called a READ operation
//                on the AMCC device.  Go figure...
//
///////////////////////////////////////////////////////////////////////////////
BOOLEAN
WriteIsDone(IN PVOID SynchronizeContext)
{
    POSR_DEVICE_EXT devExt = (POSR_DEVICE_EXT)SynchronizeContext;

    //
    // Is a WRITE operation complete on the device?
    // (Yes, the correct bit to check is _READ_COMP!)
    //
    if(devExt->IntCsr & AMCC_INT_READ_COMP)  {

        devExt->IntCsr &=  ~AMCC_INT_READ_COMP;

        return(TRUE);
    }
        
   return(FALSE);
}    

///////////////////////////////////////////////////////////////////////////////
//
//  OsrDpcForIsr
//
//      This is the DPC for ISR function.  It is called as a result of a
//      call to IoRequestDpc() in the interrupt service routine.  It handles
//      request completion, and propagation of the driver (i.e. checking the
//      queue and starting the next queued request if one is pending).
//
//  INPUTS:
//
//    Dpc - Address of our DPC Object.
//
//    Unused - Unused.
//
//    Context - Address of our device extension.
//
//  OUTPUTS:
//
//      None.
//
//  RETURNS:
//
//    None.
//
//  IRQL:
//
//    This routine is called at IRQL == IRQL_DISPATCH_LEVEL
//
//  NOTES:
//
///////////////////////////////////////////////////////////////////////////////
VOID
OsrDpcForIsr(PKDPC Dpc, PDEVICE_OBJECT DeviceObject, PIRP Unused, PVOID Context)
{
    POSR_DEVICE_EXT devExt = (POSR_DEVICE_EXT) DeviceObject->DeviceExtension;
    PLIST_ENTRY entry;
    PIRP irp;
    PVOID baseVa;
    ULONG mapRegsNeeded;
       
#if DBG
    DbgPrint("----------OSRPCI DPC\n");
#endif

    //
    // Check to see if a read or Write operation has completed.  Recall that
    // this device can have both a single read and a single write in progress
    // simultaneously.
    // 
    // For each read or write complete, we need to:
    //
    //      o See if the entire buffer has been DMA'ed.  It is possible that
    //          due to physical buffer fragmentation (since this driver does
    //          not support scatter/gather), or due to map register limitations,
    //          we have had to break the user's request up into multiple DMA
    //          transfers.
    //
    //      o If the entire buffer has not been DMA'ed, and the current request
    //          has not been cancelled, we set up another DMA transfer, starting
    //          from where the previous DMA left off. 
    //
    //      o If the entire buffer HAS been DMA'ed, or the current request has
    //          been cancelled, we complete the request with the appropriate
    //          status. We then try to remove an entry from the relevant queue
    //          and start it on the device.  If we happen to remove an IRP with
    //          the cancel flag set, we cancel it, and try to get another IRP
    //          from the queue.  Note this cancel check is required to catch
    //          the case of the IRP being cancelled while we are in the DpcForIsr.
    //  
    // Note that in our simple model of the world, transfer complete means
    // transfer SUCCESSFULLY complete.  This sample driver does not attempt
    // error detection, reporting, or recovery.
    //

    //
    // Write complete??
    //
    if( KeSynchronizeExecution(devExt->InterruptObject,
                                WriteIsDone,
                                devExt) )  {
#if DBG
        DbgPrint("---Write Done\n");
#endif

        //
        // Get the write queue lock
        //
        KeAcquireSpinLockAtDpcLevel(&devExt->WriteQueueLock);