?? fet140_ta_pwm02.s43
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#include "msp430x14x.h"
;******************************************************************************
; MSP-FET430P140 Demo - Timer_A PWM TA1-2 upmode, 32kHz ACLK
;
; Description; This program will generate a two PWM outputs on P1.2/1.3 using
; Timer_A in an upmode. The value in CCR0, 512, defines the period and the
; values in CCR1 and CCR1 the duty PWM cycles. Using 32kHz ACLK as TACLK,
; the timer period is 15.6ms with a 75% duty cycle on P1.2 and 25% on P1.3.
; ACLK = TACLK = LFXT1 = 32768, MCLK = default DCO ~ 800kHz.
; Normal mode LPM3
; //*External watch crystal on XIN XOUT is required for ACLK*//
;
; MSP430F149
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P1.2|--> CCR1 - 75% PWM
; | P1.3|--> CCR2 - 25% PWM
;
; M.Buccini
; Texas Instruments, Inc
; January 2002
;******************************************************************************
;------------------------------------------------------------------------------
ORG 01100h ; Program Start
;------------------------------------------------------------------------------
RESET mov.w #0A00h,SP ; Initialize 'F149 stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupTA mov.w #TASSEL0+TACLR,&TACTL ; ACLK, Clear TAR
SetupC0 mov.w #512-1,&CCR0 ; PWM Period
SetupC1 mov.w #OUTMOD_7,&CCTL1 ; CCR1 reset/set
mov.w #384,&CCR1 ; CCR1 PWM Duty Cycle
SetupC2 mov.w #OUTMOD_7,&CCTL2 ; CCR2 reset/set
mov.w #128,&CCR2 ; CCR2 PWM duty cycle
SetupP1 bis.b #00Ch,&P1DIR ; P1.2 and P1.3 outputs
bis.b #00Ch,&P1SEL ; P1.2 and P1.3 TA1/2 option
bis.w #MC0,&TACTL ; Start Timer_A in upmode
;
Mainloop bis.w #LPM3,SR ; Remain in LPM3
nop ; Required only for C-spy
;
;------------------------------------------------------------------------------
; Interrupt Vectors Used MSP430x13x/14x
;------------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
END
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